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14940aee45
Removed upstreamed: target/linux/mvebu/patches-5.4/001-PCI-aardvark-Wait-for-endpoint-to-be-ready-before-tr.patch target/linux/mvebu/patches-5.4/016-PCI-aardvark-Train-link-immediately-after-enabling-t.patch target/linux/mvebu/patches-5.4/017-PCI-aardvark-Improve-link-training.patch target/linux/mvebu/patches-5.4/018-PCI-aardvark-Issue-PERST-via-GPIO.patch target/linux/mvebu/patches-5.4/020-arm64-dts-marvell-armada-37xx-Set-pcie_reset_pin-to-.patch The following patch does not apply to upstream any more and needs some more work to make it work fully again. I am not sure if we are still able to set the UART to a none standard baud rate. target/linux/ath79/patches-5.4/921-serial-core-add-support-for-boot-console-with-arbitr.patch These patches needed manually changes: target/linux/generic/pending-5.4/110-ehci_hcd_ignore_oc.patch target/linux/ipq806x/patches-5.4/0065-arm-override-compiler-flags.patch target/linux/layerscape/patches-5.4/804-crypto-0016-MLKU-114-1-crypto-caam-reduce-page-0-regs-access-to-.patch target/linux/mvebu/patches-5.4/019-PCI-aardvark-Add-PHY-support.patch target/linux/octeontx/patches-5.4/0004-PCI-add-quirk-for-Gateworks-PLX-PEX860x-switch-with-.patch All others updated automatically. Compile-tested on: malta/le, armvirt/64, lantiq/xrx200 Runtime-tested on: malta/le, armvirt/64, lantiq/xrx200 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
23 lines
864 B
Diff
23 lines
864 B
Diff
From d59be41c014e2e17ea0aaa37d42f36548ad063b5 Mon Sep 17 00:00:00 2001
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From: Haiying Wang <Haiying.wang@freescale.com>
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Date: Sat, 8 Aug 2015 07:25:02 -0400
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Subject: [PATCH] arm64/pgtable: add support to map cacheable and non shareable
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memory
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Signed-off-by: Haiying Wang <Haiying.wang@freescale.com>
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---
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arch/arm64/include/asm/pgtable.h | 2 ++
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1 file changed, 2 insertions(+)
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--- a/arch/arm64/include/asm/pgtable.h
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+++ b/arch/arm64/include/asm/pgtable.h
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@@ -431,6 +431,8 @@ static inline pmd_t pmd_mkdevmap(pmd_t p
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#define pgprot_cached(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_NORMAL) | \
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PTE_PXN | PTE_UXN)
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+#define pgprot_cached_ns(prot) \
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+ __pgprot(pgprot_val(pgprot_cached(prot)) ^ PTE_SHARED)
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#define pgprot_device(prot) \
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__pgprot_modify(prot, PTE_ATTRINDX_MASK, PTE_ATTRINDX(MT_DEVICE_nGnRE) | PTE_PXN | PTE_UXN)
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/*
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