mirror of
https://github.com/openwrt/openwrt.git
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d4aad642ff
Manually rebased:
ramips/patches-5.10/810-uvc-add-iPassion-iP2970-support.patch
All other patches automatically rebased.
Signed-off-by: John Audia <therealgraysky@proton.me>
286 lines
8.2 KiB
Diff
286 lines
8.2 KiB
Diff
From 5c7d1181056feef0b58fb2f556f55e170ba5b479 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Sat, 25 Jul 2020 19:14:59 +0200
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Subject: [PATCH 01/10] drivers: thermal: tsens: Add VER_0 tsens version
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VER_0 is used to describe device based on tsens version before v0.1.
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These device are devices based on msm8960 for example apq8064 or
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ipq806x.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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Reviewed-by: Thara Gopinath <thara.gopinath@linaro.org>
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Reported-by: kernel test robot <lkp@intel.com>
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Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
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---
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drivers/thermal/qcom/tsens.c | 150 ++++++++++++++++++++++++++++-------
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drivers/thermal/qcom/tsens.h | 4 +-
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2 files changed, 124 insertions(+), 30 deletions(-)
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--- a/drivers/thermal/qcom/tsens.c
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+++ b/drivers/thermal/qcom/tsens.c
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@@ -12,6 +12,7 @@
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#include <linux/of.h>
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#include <linux/of_address.h>
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#include <linux/of_platform.h>
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+#include <linux/mfd/syscon.h>
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#include <linux/platform_device.h>
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#include <linux/pm.h>
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#include <linux/regmap.h>
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@@ -515,6 +516,15 @@ static irqreturn_t tsens_irq_thread(int
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dev_dbg(priv->dev, "[%u] %s: no violation: %d\n",
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hw_id, __func__, temp);
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}
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+
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+ if (tsens_version(priv) < VER_0_1) {
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+ /* Constraint: There is only 1 interrupt control register for all
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+ * 11 temperature sensor. So monitoring more than 1 sensor based
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+ * on interrupts will yield inconsistent result. To overcome this
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+ * issue we will monitor only sensor 0 which is the master sensor.
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+ */
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+ break;
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+ }
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}
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return IRQ_HANDLED;
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@@ -530,6 +540,13 @@ static int tsens_set_trips(void *_sensor
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int high_val, low_val, cl_high, cl_low;
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u32 hw_id = s->hw_id;
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+ if (tsens_version(priv) < VER_0_1) {
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+ /* Pre v0.1 IP had a single register for each type of interrupt
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+ * and thresholds
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+ */
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+ hw_id = 0;
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+ }
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+
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dev_dbg(dev, "[%u] %s: proposed thresholds: (%d:%d)\n",
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hw_id, __func__, low, high);
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@@ -584,18 +601,21 @@ int get_temp_tsens_valid(const struct ts
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u32 valid;
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int ret;
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- ret = regmap_field_read(priv->rf[valid_idx], &valid);
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- if (ret)
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- return ret;
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- while (!valid) {
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- /* Valid bit is 0 for 6 AHB clock cycles.
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- * At 19.2MHz, 1 AHB clock is ~60ns.
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- * We should enter this loop very, very rarely.
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- */
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- ndelay(400);
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+ /* VER_0 doesn't have VALID bit */
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+ if (tsens_version(priv) >= VER_0_1) {
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ret = regmap_field_read(priv->rf[valid_idx], &valid);
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if (ret)
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return ret;
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+ while (!valid) {
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+ /* Valid bit is 0 for 6 AHB clock cycles.
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+ * At 19.2MHz, 1 AHB clock is ~60ns.
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+ * We should enter this loop very, very rarely.
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+ */
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+ ndelay(400);
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+ ret = regmap_field_read(priv->rf[valid_idx], &valid);
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+ if (ret)
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+ return ret;
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+ }
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}
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/* Valid bit is set, OK to read the temperature */
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@@ -608,15 +628,29 @@ int get_temp_common(const struct tsens_s
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{
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struct tsens_priv *priv = s->priv;
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int hw_id = s->hw_id;
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- int last_temp = 0, ret;
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+ int last_temp = 0, ret, trdy;
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+ unsigned long timeout;
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- ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
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- if (ret)
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- return ret;
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+ timeout = jiffies + usecs_to_jiffies(TIMEOUT_US);
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+ do {
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+ if (tsens_version(priv) == VER_0) {
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+ ret = regmap_field_read(priv->rf[TRDY], &trdy);
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+ if (ret)
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+ return ret;
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+ if (!trdy)
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+ continue;
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+ }
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- *temp = code_to_degc(last_temp, s) * 1000;
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+ ret = regmap_field_read(priv->rf[LAST_TEMP_0 + hw_id], &last_temp);
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+ if (ret)
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+ return ret;
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- return 0;
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+ *temp = code_to_degc(last_temp, s) * 1000;
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+
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+ return 0;
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+ } while (time_before(jiffies, timeout));
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+
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+ return -ETIMEDOUT;
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}
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#ifdef CONFIG_DEBUG_FS
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@@ -738,19 +772,34 @@ int __init init_common(struct tsens_priv
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priv->tm_offset = 0x1000;
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}
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- res = platform_get_resource(op, IORESOURCE_MEM, 0);
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- tm_base = devm_ioremap_resource(dev, res);
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- if (IS_ERR(tm_base)) {
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- ret = PTR_ERR(tm_base);
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- goto err_put_device;
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+ if (tsens_version(priv) >= VER_0_1) {
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+ res = platform_get_resource(op, IORESOURCE_MEM, 0);
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+ tm_base = devm_ioremap_resource(dev, res);
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+ if (IS_ERR(tm_base)) {
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+ ret = PTR_ERR(tm_base);
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+ goto err_put_device;
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+ }
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+
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+ priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
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+ } else { /* VER_0 share the same gcc regs using a syscon */
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+ struct device *parent = priv->dev->parent;
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+
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+ if (parent)
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+ priv->tm_map = syscon_node_to_regmap(parent->of_node);
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}
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- priv->tm_map = devm_regmap_init_mmio(dev, tm_base, &tsens_config);
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- if (IS_ERR(priv->tm_map)) {
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- ret = PTR_ERR(priv->tm_map);
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+ if (IS_ERR_OR_NULL(priv->tm_map)) {
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+ if (!priv->tm_map)
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+ ret = -ENODEV;
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+ else
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+ ret = PTR_ERR(priv->tm_map);
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goto err_put_device;
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}
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+ /* VER_0 have only tm_map */
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+ if (!priv->srot_map)
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+ priv->srot_map = priv->tm_map;
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+
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if (tsens_version(priv) > VER_0_1) {
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for (i = VER_MAJOR; i <= VER_STEP; i++) {
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priv->rf[i] = devm_regmap_field_alloc(dev, priv->srot_map,
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@@ -771,6 +820,10 @@ int __init init_common(struct tsens_priv
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ret = PTR_ERR(priv->rf[TSENS_EN]);
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goto err_put_device;
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}
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+ /* in VER_0 TSENS need to be explicitly enabled */
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+ if (tsens_version(priv) == VER_0)
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+ regmap_field_write(priv->rf[TSENS_EN], 1);
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+
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ret = regmap_field_read(priv->rf[TSENS_EN], &enabled);
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if (ret)
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goto err_put_device;
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@@ -793,6 +846,19 @@ int __init init_common(struct tsens_priv
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goto err_put_device;
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}
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+ priv->rf[TSENS_SW_RST] =
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+ devm_regmap_field_alloc(dev, priv->srot_map, priv->fields[TSENS_SW_RST]);
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+ if (IS_ERR(priv->rf[TSENS_SW_RST])) {
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+ ret = PTR_ERR(priv->rf[TSENS_SW_RST]);
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+ goto err_put_device;
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+ }
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+
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+ priv->rf[TRDY] = devm_regmap_field_alloc(dev, priv->tm_map, priv->fields[TRDY]);
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+ if (IS_ERR(priv->rf[TRDY])) {
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+ ret = PTR_ERR(priv->rf[TRDY]);
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+ goto err_put_device;
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+ }
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+
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/* This loop might need changes if enum regfield_ids is reordered */
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for (j = LAST_TEMP_0; j <= UP_THRESH_15; j += 16) {
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for (i = 0; i < priv->feat->max_sensors; i++) {
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@@ -808,7 +874,7 @@ int __init init_common(struct tsens_priv
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}
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}
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- if (priv->feat->crit_int) {
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+ if (priv->feat->crit_int || tsens_version(priv) < VER_0_1) {
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/* Loop might need changes if enum regfield_ids is reordered */
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for (j = CRITICAL_STATUS_0; j <= CRIT_THRESH_15; j += 16) {
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for (i = 0; i < priv->feat->max_sensors; i++) {
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@@ -846,7 +912,11 @@ int __init init_common(struct tsens_priv
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}
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spin_lock_init(&priv->ul_lock);
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- tsens_enable_irq(priv);
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+
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+ /* VER_0 interrupt doesn't need to be enabled */
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+ if (tsens_version(priv) >= VER_0_1)
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+ tsens_enable_irq(priv);
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+
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tsens_debug_init(op);
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err_put_device:
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@@ -951,10 +1021,19 @@ static int tsens_register_irq(struct tse
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if (irq == -ENXIO)
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ret = 0;
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} else {
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- ret = devm_request_threaded_irq(&pdev->dev, irq,
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- NULL, thread_fn,
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- IRQF_ONESHOT,
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- dev_name(&pdev->dev), priv);
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+ /* VER_0 interrupt is TRIGGER_RISING, VER_0_1 and up is ONESHOT */
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+ if (tsens_version(priv) == VER_0)
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+ ret = devm_request_threaded_irq(&pdev->dev, irq,
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+ thread_fn, NULL,
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+ IRQF_TRIGGER_RISING,
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+ dev_name(&pdev->dev),
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+ priv);
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+ else
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+ ret = devm_request_threaded_irq(&pdev->dev, irq, NULL,
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+ thread_fn, IRQF_ONESHOT,
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+ dev_name(&pdev->dev),
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+ priv);
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+
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if (ret)
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dev_err(&pdev->dev, "%s: failed to get irq\n",
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__func__);
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@@ -983,6 +1062,19 @@ static int tsens_register(struct tsens_p
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priv->ops->enable(priv, i);
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}
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+ /* VER_0 require to set MIN and MAX THRESH
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+ * These 2 regs are set using the:
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+ * - CRIT_THRESH_0 for MAX THRESH hardcoded to 120°C
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+ * - CRIT_THRESH_1 for MIN THRESH hardcoded to 0°C
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+ */
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+ if (tsens_version(priv) < VER_0_1) {
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+ regmap_field_write(priv->rf[CRIT_THRESH_0],
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+ tsens_mC_to_hw(priv->sensor, 120000));
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+
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+ regmap_field_write(priv->rf[CRIT_THRESH_1],
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+ tsens_mC_to_hw(priv->sensor, 0));
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+ }
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+
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ret = tsens_register_irq(priv, "uplow", tsens_irq_thread);
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if (ret < 0)
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return ret;
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--- a/drivers/thermal/qcom/tsens.h
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+++ b/drivers/thermal/qcom/tsens.h
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@@ -13,6 +13,7 @@
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#define CAL_DEGC_PT2 120
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#define SLOPE_FACTOR 1000
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#define SLOPE_DEFAULT 3200
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+#define TIMEOUT_US 100
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#define THRESHOLD_MAX_ADC_CODE 0x3ff
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#define THRESHOLD_MIN_ADC_CODE 0x0
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@@ -25,7 +26,8 @@ struct tsens_priv;
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/* IP version numbers in ascending order */
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enum tsens_ver {
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- VER_0_1 = 0,
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+ VER_0 = 0,
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+ VER_0_1,
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VER_1_X,
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VER_2_X,
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};
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