mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-19 21:58:04 +00:00
85 lines
3.5 KiB
Diff
85 lines
3.5 KiB
Diff
From 194ec04b3a9e7fa97d1fbef296410631bc3cf1c8 Mon Sep 17 00:00:00 2001
|
|
From: Chuanhong Guo <gch981213@gmail.com>
|
|
Date: Sun, 20 Mar 2022 18:00:00 +0800
|
|
Subject: [PATCH 4/5] mtd: spinand: gigadevice: add support for GD5F{2,
|
|
4}GQ5xExxG
|
|
|
|
Add support for:
|
|
GD5F2GQ5{U,R}ExxG
|
|
GD5F4GQ6{U,R}ExxG
|
|
|
|
These chips uses 4 dummy bytes for quad io and 2 dummy bytes for dual io.
|
|
Besides that and memory layout, they are identical to their 1G variant.
|
|
|
|
Signed-off-by: Chuanhong Guo <gch981213@gmail.com>
|
|
Signed-off-by: Miquel Raynal <miquel.raynal@bootlin.com>
|
|
Link: https://lore.kernel.org/linux-mtd/20220320100001.247905-5-gch981213@gmail.com
|
|
---
|
|
drivers/mtd/nand/spi/gigadevice.c | 48 +++++++++++++++++++++++++++++++
|
|
1 file changed, 48 insertions(+)
|
|
|
|
--- a/drivers/mtd/nand/spi/gigadevice.c
|
|
+++ b/drivers/mtd/nand/spi/gigadevice.c
|
|
@@ -47,6 +47,14 @@ static SPINAND_OP_VARIANTS(read_cache_va
|
|
SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
|
|
SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
|
|
|
|
+static SPINAND_OP_VARIANTS(read_cache_variants_2gq5,
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 4, NULL, 0),
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_DUALIO_OP(0, 2, NULL, 0),
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_X2_OP(0, 1, NULL, 0),
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_OP(true, 0, 1, NULL, 0),
|
|
+ SPINAND_PAGE_READ_FROM_CACHE_OP(false, 0, 1, NULL, 0));
|
|
+
|
|
static SPINAND_OP_VARIANTS(write_cache_variants,
|
|
SPINAND_PROG_LOAD_X4(true, 0, NULL, 0),
|
|
SPINAND_PROG_LOAD(true, 0, NULL, 0));
|
|
@@ -393,6 +401,46 @@ static const struct spinand_info gigadev
|
|
&write_cache_variants,
|
|
&update_cache_variants),
|
|
SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+ SPINAND_INFO("GD5F2GQ5UExxG",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x52),
|
|
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+ SPINAND_INFO("GD5F2GQ5RExxG",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x42),
|
|
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 1, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+ SPINAND_INFO("GD5F4GQ6UExxG",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x55),
|
|
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
+ SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
+ gd5fxgq5xexxg_ecc_get_status)),
|
|
+ SPINAND_INFO("GD5F4GQ6RExxG",
|
|
+ SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x45),
|
|
+ NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 1, 2, 1),
|
|
+ NAND_ECCREQ(4, 512),
|
|
+ SPINAND_INFO_OP_VARIANTS(&read_cache_variants_2gq5,
|
|
+ &write_cache_variants,
|
|
+ &update_cache_variants),
|
|
+ SPINAND_HAS_QE_BIT,
|
|
SPINAND_ECCINFO(&gd5fxgqx_variant2_ooblayout,
|
|
gd5fxgq5xexxg_ecc_get_status)),
|
|
};
|