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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
230 lines
8.3 KiB
Diff
230 lines
8.3 KiB
Diff
From 474b608dee5e6285dd1981b00ab568a2f7f15fd0 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Wed, 10 Aug 2022 23:02:06 -0500
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Subject: [PATCH 106/117] phy: allwinner: phy-sun6i-mipi-dphy: Add the A100
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DPHY variant
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A100 features an updated DPHY, which moves PLL control inside the DPHY
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register space (previously the PLL was controlled from the CCU). It also
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requires a modified analog power-on sequence. This "combo PHY" can also
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be used as an LVDS PHY, but that is not yet supported by the driver.
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Cover-letter:
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phy: allwinner: phy-sun6i-mipi-dphy: Add the A100 DPHY
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This series adds support for the updated DPHY found in a couple of
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recent Allwinner SoCs. The first three patches fix an omission in the
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existing binding. The remaining patches add the new hardware variant.
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END
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Series-to: Kishon Vijay Abraham I <kishon@ti.com>
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Series-to: Vinod Koul <vkoul@kernel.org>
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Series-to: Chen-Yu Tsai <wens@csie.org>
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Series-to: Jernej Skrabec <jernej.skrabec@gmail.com>
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Series-to: Maxime Ripard <mripard@kernel.org>
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Series-cc: Paul Kocialkowski <paul.kocialkowski@bootlin.com>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/phy/allwinner/phy-sun6i-mipi-dphy.c | 143 +++++++++++++++++++-
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1 file changed, 142 insertions(+), 1 deletion(-)
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--- a/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
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+++ b/drivers/phy/allwinner/phy-sun6i-mipi-dphy.c
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@@ -70,11 +70,19 @@
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#define SUN6I_DPHY_ANA0_REG 0x4c
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#define SUN6I_DPHY_ANA0_REG_PWS BIT(31)
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+#define SUN6I_DPHY_ANA0_REG_PWEND BIT(30)
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+#define SUN6I_DPHY_ANA0_REG_PWENC BIT(29)
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#define SUN6I_DPHY_ANA0_REG_DMPC BIT(28)
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#define SUN6I_DPHY_ANA0_REG_DMPD(n) (((n) & 0xf) << 24)
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+#define SUN6I_DPHY_ANA0_REG_SRXDT(n) (((n) & 0xf) << 20)
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+#define SUN6I_DPHY_ANA0_REG_SRXCK(n) (((n) & 0xf) << 16)
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+#define SUN6I_DPHY_ANA0_REG_SDIV2 BIT(15)
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#define SUN6I_DPHY_ANA0_REG_SLV(n) (((n) & 7) << 12)
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#define SUN6I_DPHY_ANA0_REG_DEN(n) (((n) & 0xf) << 8)
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+#define SUN6I_DPHY_ANA0_REG_PLR(n) (((n) & 0xf) << 4)
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#define SUN6I_DPHY_ANA0_REG_SFB(n) (((n) & 3) << 2)
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+#define SUN6I_DPHY_ANA0_REG_RSD BIT(1)
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+#define SUN6I_DPHY_ANA0_REG_SELSCK BIT(0)
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#define SUN6I_DPHY_ANA1_REG 0x50
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#define SUN6I_DPHY_ANA1_REG_VTTMODE BIT(31)
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@@ -97,8 +105,13 @@
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#define SUN6I_DPHY_ANA3_EN_LDOR BIT(18)
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#define SUN6I_DPHY_ANA4_REG 0x5c
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+#define SUN6I_DPHY_ANA4_REG_EN_MIPI BIT(31)
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+#define SUN6I_DPHY_ANA4_REG_EN_COMTEST BIT(30)
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+#define SUN6I_DPHY_ANA4_REG_COMTEST(n) (((n) & 3) << 28)
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+#define SUN6I_DPHY_ANA4_REG_IB(n) (((n) & 3) << 25)
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#define SUN6I_DPHY_ANA4_REG_DMPLVC BIT(24)
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#define SUN6I_DPHY_ANA4_REG_DMPLVD(n) (((n) & 0xf) << 20)
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+#define SUN6I_DPHY_ANA4_REG_VTT_SET(n) (((n) & 0x7) << 17)
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#define SUN6I_DPHY_ANA4_REG_CKDV(n) (((n) & 0x1f) << 12)
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#define SUN6I_DPHY_ANA4_REG_TMSC(n) (((n) & 3) << 10)
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#define SUN6I_DPHY_ANA4_REG_TMSD(n) (((n) & 3) << 8)
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@@ -109,6 +122,56 @@
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#define SUN6I_DPHY_DBG5_REG 0xf4
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+#define SUN50I_DPHY_TX_SLEW_REG0 0xf8
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+#define SUN50I_DPHY_TX_SLEW_REG1 0xfc
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+#define SUN50I_DPHY_TX_SLEW_REG2 0x100
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+
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+#define SUN50I_DPHY_PLL_REG0 0x104
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+#define SUN50I_DPHY_PLL_REG0_CP36_EN BIT(23)
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+#define SUN50I_DPHY_PLL_REG0_LDO_EN BIT(22)
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+#define SUN50I_DPHY_PLL_REG0_EN_LVS BIT(21)
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+#define SUN50I_DPHY_PLL_REG0_PLL_EN BIT(20)
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+#define SUN50I_DPHY_PLL_REG0_P(n) (((n) & 0xf) << 16)
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+#define SUN50I_DPHY_PLL_REG0_N(n) (((n) & 0xff) << 8)
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+#define SUN50I_DPHY_PLL_REG0_NDET BIT(7)
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+#define SUN50I_DPHY_PLL_REG0_TDIV BIT(6)
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+#define SUN50I_DPHY_PLL_REG0_M0(n) (((n) & 3) << 4)
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+#define SUN50I_DPHY_PLL_REG0_M1(n) ((n) & 0xf)
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+
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+#define SUN50I_DPHY_PLL_REG1 0x108
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+#define SUN50I_DPHY_PLL_REG1_UNLOCK_MDSEL(n) (((n) & 3) << 14)
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+#define SUN50I_DPHY_PLL_REG1_LOCKMDSEL BIT(13)
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+#define SUN50I_DPHY_PLL_REG1_LOCKDET_EN BIT(12)
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+#define SUN50I_DPHY_PLL_REG1_VSETA(n) (((n) & 0x7) << 9)
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+#define SUN50I_DPHY_PLL_REG1_VSETD(n) (((n) & 0x7) << 6)
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+#define SUN50I_DPHY_PLL_REG1_LPF_SW BIT(5)
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+#define SUN50I_DPHY_PLL_REG1_ICP_SEL(n) (((n) & 3) << 3)
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+#define SUN50I_DPHY_PLL_REG1_ATEST_SEL(n) (((n) & 3) << 1)
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+#define SUN50I_DPHY_PLL_REG1_TEST_EN BIT(0)
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+
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+#define SUN50I_DPHY_PLL_REG2 0x10c
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+#define SUN50I_DPHY_PLL_REG2_SDM_EN BIT(31)
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+#define SUN50I_DPHY_PLL_REG2_FF_EN BIT(30)
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+#define SUN50I_DPHY_PLL_REG2_SS_EN BIT(29)
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+#define SUN50I_DPHY_PLL_REG2_SS_FRAC(n) (((n) & 0x1ff) << 20)
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+#define SUN50I_DPHY_PLL_REG2_SS_INT(n) (((n) & 0xff) << 12)
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+#define SUN50I_DPHY_PLL_REG2_FRAC(n) ((n) & 0xfff)
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+
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+#define SUN50I_COMBO_PHY_REG0 0x110
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+#define SUN50I_COMBO_PHY_REG0_EN_TEST_COMBOLDO BIT(5)
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+#define SUN50I_COMBO_PHY_REG0_EN_TEST_0P8 BIT(4)
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+#define SUN50I_COMBO_PHY_REG0_EN_MIPI BIT(3)
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+#define SUN50I_COMBO_PHY_REG0_EN_LVDS BIT(2)
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+#define SUN50I_COMBO_PHY_REG0_EN_COMBOLDO BIT(1)
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+#define SUN50I_COMBO_PHY_REG0_EN_CP BIT(0)
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+
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+#define SUN50I_COMBO_PHY_REG1 0x114
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+#define SUN50I_COMBO_PHY_REG2_REG_VREF1P6(n) (((n) & 0x7) << 4)
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+#define SUN50I_COMBO_PHY_REG2_REG_VREF0P8(n) ((n) & 0x7)
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+
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+#define SUN50I_COMBO_PHY_REG2 0x118
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+#define SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(n) ((n) & 0xff)
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+
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enum sun6i_dphy_direction {
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SUN6I_DPHY_DIRECTION_TX,
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SUN6I_DPHY_DIRECTION_RX,
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@@ -196,6 +259,76 @@ static void sun6i_a31_mipi_dphy_tx_power
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udelay(1);
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}
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+static void sun50i_a100_mipi_dphy_tx_power_on(struct sun6i_dphy *dphy)
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+{
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+ unsigned long mipi_symbol_rate = dphy->config.hs_clk_rate;
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+ unsigned int div, n;
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+
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+ regmap_write(dphy->regs, SUN6I_DPHY_ANA4_REG,
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+ SUN6I_DPHY_ANA4_REG_IB(2) |
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+ SUN6I_DPHY_ANA4_REG_DMPLVD(4) |
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+ SUN6I_DPHY_ANA4_REG_VTT_SET(3) |
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+ SUN6I_DPHY_ANA4_REG_CKDV(3) |
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+ SUN6I_DPHY_ANA4_REG_TMSD(1) |
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+ SUN6I_DPHY_ANA4_REG_TMSC(1) |
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+ SUN6I_DPHY_ANA4_REG_TXPUSD(2) |
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+ SUN6I_DPHY_ANA4_REG_TXPUSC(3) |
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+ SUN6I_DPHY_ANA4_REG_TXDNSD(2) |
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+ SUN6I_DPHY_ANA4_REG_TXDNSC(3));
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+
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+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
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+ SUN6I_DPHY_ANA2_EN_CK_CPU,
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+ SUN6I_DPHY_ANA2_EN_CK_CPU);
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+
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+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA2_REG,
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+ SUN6I_DPHY_ANA2_REG_ENIB,
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+ SUN6I_DPHY_ANA2_REG_ENIB);
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+
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+ regmap_write(dphy->regs, SUN6I_DPHY_ANA3_REG,
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+ SUN6I_DPHY_ANA3_EN_LDOR |
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+ SUN6I_DPHY_ANA3_EN_LDOC |
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+ SUN6I_DPHY_ANA3_EN_LDOD);
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+
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+ regmap_write(dphy->regs, SUN6I_DPHY_ANA0_REG,
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+ SUN6I_DPHY_ANA0_REG_PLR(4) |
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+ SUN6I_DPHY_ANA0_REG_SFB(1));
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+
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+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG0,
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+ SUN50I_COMBO_PHY_REG0_EN_CP);
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+
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+ /* Choose a divider to limit the VCO frequency to around 2 GHz. */
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+ div = 16 >> order_base_2(DIV_ROUND_UP(mipi_symbol_rate, 264000000));
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+ n = mipi_symbol_rate * div / 24000000;
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+
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+ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG0,
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+ SUN50I_DPHY_PLL_REG0_CP36_EN |
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+ SUN50I_DPHY_PLL_REG0_LDO_EN |
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+ SUN50I_DPHY_PLL_REG0_EN_LVS |
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+ SUN50I_DPHY_PLL_REG0_PLL_EN |
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+ SUN50I_DPHY_PLL_REG0_NDET |
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+ SUN50I_DPHY_PLL_REG0_P((div - 1) % 8) |
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+ SUN50I_DPHY_PLL_REG0_N(n) |
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+ SUN50I_DPHY_PLL_REG0_M0((div - 1) / 8) |
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+ SUN50I_DPHY_PLL_REG0_M1(2));
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+
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+ /* Disable sigma-delta modulation. */
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+ regmap_write(dphy->regs, SUN50I_DPHY_PLL_REG2, 0);
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+
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+ regmap_update_bits(dphy->regs, SUN6I_DPHY_ANA4_REG,
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+ SUN6I_DPHY_ANA4_REG_EN_MIPI,
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+ SUN6I_DPHY_ANA4_REG_EN_MIPI);
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+
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+ regmap_update_bits(dphy->regs, SUN50I_COMBO_PHY_REG0,
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+ SUN50I_COMBO_PHY_REG0_EN_MIPI |
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+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO,
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+ SUN50I_COMBO_PHY_REG0_EN_MIPI |
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+ SUN50I_COMBO_PHY_REG0_EN_COMBOLDO);
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+
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+ regmap_write(dphy->regs, SUN50I_COMBO_PHY_REG2,
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+ SUN50I_COMBO_PHY_REG2_HS_STOP_DLY(20));
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+ udelay(1);
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+}
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+
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static int sun6i_dphy_tx_power_on(struct sun6i_dphy *dphy)
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{
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u8 lanes_mask = GENMASK(dphy->config.lanes - 1, 0);
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@@ -408,7 +541,7 @@ static const struct regmap_config sun6i_
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.reg_bits = 32,
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.val_bits = 32,
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.reg_stride = 4,
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- .max_register = SUN6I_DPHY_DBG5_REG,
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+ .max_register = SUN50I_COMBO_PHY_REG2,
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.name = "mipi-dphy",
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};
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@@ -483,11 +616,19 @@ static const struct sun6i_dphy_variant s
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.supports_rx = true,
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};
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+static const struct sun6i_dphy_variant sun50i_a100_mipi_dphy_variant = {
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+ .tx_power_on = sun50i_a100_mipi_dphy_tx_power_on,
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+};
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+
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static const struct of_device_id sun6i_dphy_of_table[] = {
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{
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.compatible = "allwinner,sun6i-a31-mipi-dphy",
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.data = &sun6i_a31_mipi_dphy_variant,
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},
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+ {
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+ .compatible = "allwinner,sun50i-a100-mipi-dphy",
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+ .data = &sun50i_a100_mipi_dphy_variant,
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+ },
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{ }
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};
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MODULE_DEVICE_TABLE(of, sun6i_dphy_of_table);
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