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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
35 lines
1.4 KiB
Diff
35 lines
1.4 KiB
Diff
From c7fa1be12bf0ef02f5557dd1d1100d25af4e34f5 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 7 Aug 2022 11:00:12 -0500
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Subject: [PATCH 102/117] dt-bindings: sun6i-a31-mipi-dphy: Add the A100 DPHY
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variant
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A100 features an updated DPHY, which moves PLL control inside the DPHY
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register space. (Previously PLL-MIPI was controlled from the CCU. This
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does not affect the "clocks" property because the link between PLL-MIPI
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and the DPHY was never represented in the devicetree.) It also requires
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a modified analog power-on sequence. Finally, the new DPHY adds support
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for operating as an LVDS PHY. D1 uses this same variant.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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.../bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml | 4 ++++
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1 file changed, 4 insertions(+)
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--- a/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
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+++ b/Documentation/devicetree/bindings/phy/allwinner,sun6i-a31-mipi-dphy.yaml
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@@ -17,9 +17,13 @@ properties:
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compatible:
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oneOf:
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- const: allwinner,sun6i-a31-mipi-dphy
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+ - const: allwinner,sun50i-a100-mipi-dphy
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- items:
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- const: allwinner,sun50i-a64-mipi-dphy
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- const: allwinner,sun6i-a31-mipi-dphy
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+ - items:
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+ - const: allwinner,sun20i-d1-mipi-dphy
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+ - const: allwinner,sun50i-a100-mipi-dphy
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reg:
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maxItems: 1
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