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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
23 lines
839 B
Diff
23 lines
839 B
Diff
From 11d78fce09e80ec246016c19ecc28a724e1e5530 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Fri, 12 Aug 2022 02:25:55 -0500
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Subject: [PATCH 101/117] arm64: dts: allwinner: a64: Add DPHY interrupt
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The DPHY has an interrupt line which is shared with the DSI controller.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi | 1 +
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1 file changed, 1 insertion(+)
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--- a/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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+++ b/arch/arm64/boot/dts/allwinner/sun50i-a64.dtsi
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@@ -1199,6 +1199,7 @@
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compatible = "allwinner,sun50i-a64-mipi-dphy",
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"allwinner,sun6i-a31-mipi-dphy";
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reg = <0x01ca1000 0x1000>;
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+ interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
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clocks = <&ccu CLK_BUS_MIPI_DSI>,
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<&ccu CLK_DSI_DPHY>;
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clock-names = "bus", "mod";
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