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13cdc8955c
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.1.80 Manually rebased: generic/hack-6.1/650-netfilter-add-xt_FLOWOFFLOAD-target.patch[1] All other patches automatically rebased. 1. Acknowledgement to @heheb and @DragonBluep. Upstream commit for ref: https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.1.80&id=9c5662e95a8dcc232c3ef4deb21033badcd260f6 Build system: x86/64 Build-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3 Run-tested: x86/64/AMD Cezanne, ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me>
117 lines
3.6 KiB
Diff
117 lines
3.6 KiB
Diff
From b42a9e0cf6b0ca78b4ef5310de967d515a3cca03 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 13 Jun 2021 23:53:16 -0500
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Subject: [PATCH 070/117] ASoC: sun4i-spdif: Add support for separate RX/TX
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clocks
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On older variants of the hardware, the RX and TX blocks share a single
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module clock, named "spdif" in the DT binding. The D1 variant has
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separate RX and TX clocks, so the TX module clock is named "tx" in the
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binding. To support this, supply the clock name in the quirks structure.
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Since the driver supports only TX, only the TX clock name is needed.
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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sound/soc/sunxi/sun4i-spdif.c | 24 +++++++++++++++---------
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1 file changed, 15 insertions(+), 9 deletions(-)
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--- a/sound/soc/sunxi/sun4i-spdif.c
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+++ b/sound/soc/sunxi/sun4i-spdif.c
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@@ -169,18 +169,20 @@
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/**
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* struct sun4i_spdif_quirks - Differences between SoC variants.
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*
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+ * @tx_clk_name: firmware name for the TX clock reference.
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* @reg_dac_txdata: TX FIFO offset for DMA config.
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* @val_fctl_ftx: TX FIFO flush bitmask.
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*/
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struct sun4i_spdif_quirks {
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+ const char *tx_clk_name;
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unsigned int reg_dac_txdata;
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unsigned int val_fctl_ftx;
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};
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struct sun4i_spdif_dev {
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struct platform_device *pdev;
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- struct clk *spdif_clk;
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struct clk *apb_clk;
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+ struct clk *tx_clk;
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struct reset_control *rst;
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struct snd_soc_dai_driver cpu_dai_drv;
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struct regmap *regmap;
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@@ -313,7 +315,7 @@ static int sun4i_spdif_hw_params(struct
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return -EINVAL;
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}
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- ret = clk_set_rate(host->spdif_clk, mclk);
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+ ret = clk_set_rate(host->tx_clk, mclk);
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if (ret < 0) {
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dev_err(&pdev->dev,
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"Setting SPDIF clock rate for %d Hz failed!\n", mclk);
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@@ -537,21 +539,25 @@ static struct snd_soc_dai_driver sun4i_s
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};
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static const struct sun4i_spdif_quirks sun4i_a10_spdif_quirks = {
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+ .tx_clk_name = "spdif",
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.reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
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.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
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};
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static const struct sun4i_spdif_quirks sun6i_a31_spdif_quirks = {
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+ .tx_clk_name = "spdif",
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.reg_dac_txdata = SUN4I_SPDIF_TXFIFO,
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.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
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};
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static const struct sun4i_spdif_quirks sun8i_h3_spdif_quirks = {
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+ .tx_clk_name = "spdif",
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.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
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.val_fctl_ftx = SUN4I_SPDIF_FCTL_FTX,
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};
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static const struct sun4i_spdif_quirks sun50i_h6_spdif_quirks = {
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+ .tx_clk_name = "spdif",
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.reg_dac_txdata = SUN8I_SPDIF_TXFIFO,
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.val_fctl_ftx = SUN50I_H6_SPDIF_FCTL_FTX,
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};
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@@ -591,7 +597,7 @@ static int sun4i_spdif_runtime_suspend(s
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{
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struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
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- clk_disable_unprepare(host->spdif_clk);
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+ clk_disable_unprepare(host->tx_clk);
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clk_disable_unprepare(host->apb_clk);
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return 0;
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@@ -602,12 +608,12 @@ static int sun4i_spdif_runtime_resume(st
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struct sun4i_spdif_dev *host = dev_get_drvdata(dev);
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int ret;
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- ret = clk_prepare_enable(host->spdif_clk);
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+ ret = clk_prepare_enable(host->tx_clk);
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if (ret)
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return ret;
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ret = clk_prepare_enable(host->apb_clk);
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if (ret)
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- clk_disable_unprepare(host->spdif_clk);
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+ clk_disable_unprepare(host->tx_clk);
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return ret;
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}
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@@ -655,10 +661,10 @@ static int sun4i_spdif_probe(struct plat
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return PTR_ERR(host->apb_clk);
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}
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- host->spdif_clk = devm_clk_get(&pdev->dev, "spdif");
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- if (IS_ERR(host->spdif_clk)) {
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- dev_err(&pdev->dev, "failed to get a spdif clock.\n");
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- return PTR_ERR(host->spdif_clk);
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+ host->tx_clk = devm_clk_get(&pdev->dev, quirks->tx_clk_name);
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+ if (IS_ERR(host->tx_clk)) {
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+ dev_err(&pdev->dev, "failed to get TX module clock.\n");
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+ return PTR_ERR(host->tx_clk);
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}
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host->dma_params_tx.addr = res->start + quirks->reg_dac_txdata;
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