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https://github.com/openwrt/openwrt.git
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7bbf4117c6
This add support for kernel 4.9 to the ar71xx target. It was compile tested with the generic, NAND and mikrotik subtarget. Multiple members of the community tested it on their boards and did not report any major problem so far. Especially the NAND part received some changes to adapt to the new kernel APIs. The serial driver hack used for the Arduino Yun was not ported because the kernel changed there a lot. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
193 lines
4.5 KiB
Diff
193 lines
4.5 KiB
Diff
--- a/arch/mips/ath79/dev-wmac.c
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+++ b/arch/mips/ath79/dev-wmac.c
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@@ -166,6 +166,149 @@ static void qca955x_wmac_setup(void)
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ath79_wmac_data.is_clk_25mhz = true;
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}
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+#define AR93XX_WMAC_SIZE \
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+ (soc_is_ar934x() ? AR934X_WMAC_SIZE : AR933X_WMAC_SIZE)
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+#define AR93XX_WMAC_BASE \
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+ (soc_is_ar934x() ? AR934X_WMAC_BASE : AR933X_WMAC_BASE)
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+
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+#define AR93XX_OTP_BASE \
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+ (soc_is_ar934x() ? AR934X_OTP_BASE : AR9300_OTP_BASE)
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+#define AR93XX_OTP_STATUS \
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+ (soc_is_ar934x() ? AR934X_OTP_STATUS : AR9300_OTP_STATUS)
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+#define AR93XX_OTP_READ_DATA \
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+ (soc_is_ar934x() ? AR934X_OTP_READ_DATA : AR9300_OTP_READ_DATA)
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+
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+static bool __init
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+ar93xx_wmac_otp_read_word(void __iomem *base, int addr, u32 *data)
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+{
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+ int timeout = 1000;
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+ u32 val;
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+
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+ __raw_readl(base + AR93XX_OTP_BASE + (4 * addr));
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+ while (timeout--) {
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+ val = __raw_readl(base + AR93XX_OTP_STATUS);
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+ if ((val & AR9300_OTP_STATUS_TYPE) == AR9300_OTP_STATUS_VALID)
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ if (!timeout)
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+ return false;
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+
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+ *data = __raw_readl(base + AR93XX_OTP_READ_DATA);
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+ return true;
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+}
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+
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+static bool __init
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+ar93xx_wmac_otp_read(void __iomem *base, int addr, u8 *dest, int len)
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+{
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+ u32 data;
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+ int i;
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+
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+ for (i = 0; i < len; i++) {
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+ int offset = 8 * ((addr - i) % 4);
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+
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+ if (!ar93xx_wmac_otp_read_word(base, (addr - i) / 4, &data))
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+ return false;
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+
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+ dest[i] = (data >> offset) & 0xff;
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+ }
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+
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+ return true;
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+}
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+
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+static bool __init
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+ar93xx_wmac_otp_uncompress(void __iomem *base, int addr, int len, u8 *dest,
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+ int dest_start, int dest_len)
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+{
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+ int dest_bytes = 0;
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+ int offset = 0;
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+ int end = addr - len;
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+ u8 hdr[2];
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+
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+ while (addr > end) {
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+ if (!ar93xx_wmac_otp_read(base, addr, hdr, 2))
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+ return false;
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+
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+ addr -= 2;
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+ offset += hdr[0];
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+
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+ if (offset <= dest_start + dest_len &&
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+ offset + len >= dest_start) {
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+ int data_offset = 0;
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+ int dest_offset = 0;
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+ int copy_len;
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+
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+ if (offset < dest_start)
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+ data_offset = dest_start - offset;
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+ else
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+ dest_offset = offset - dest_start;
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+
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+ copy_len = len - data_offset;
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+ if (copy_len > dest_len - dest_offset)
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+ copy_len = dest_len - dest_offset;
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+
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+ ar93xx_wmac_otp_read(base, addr - data_offset,
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+ dest + dest_offset,
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+ copy_len);
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+
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+ dest_bytes += copy_len;
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+ }
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+ addr -= hdr[1];
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+ }
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+ return !!dest_bytes;
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+}
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+
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+bool __init ar93xx_wmac_read_mac_address(u8 *dest)
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+{
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+ void __iomem *base;
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+ bool ret = false;
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+ int addr = 0x1ff;
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+ unsigned int len;
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+ u32 hdr_u32;
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+ u8 *hdr = (u8 *) &hdr_u32;
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+ u8 mac[6] = { 0x00, 0x02, 0x03, 0x04, 0x05, 0x06 };
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+ int mac_start = 2, mac_end = 8;
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+
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+ BUG_ON(!soc_is_ar933x() && !soc_is_ar934x());
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+ base = ioremap_nocache(AR93XX_WMAC_BASE, AR93XX_WMAC_SIZE);
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+ while (addr > sizeof(hdr_u32)) {
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+ if (!ar93xx_wmac_otp_read(base, addr, hdr, sizeof(hdr_u32)))
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+ break;
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+
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+ if (hdr_u32 == 0 || hdr_u32 == ~0)
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+ break;
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+
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+ len = (hdr[1] << 4) | (hdr[2] >> 4);
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+ addr -= 4;
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+
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+ switch (hdr[0] >> 5) {
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+ case 0:
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+ if (len < mac_end)
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+ break;
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+
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+ ar93xx_wmac_otp_read(base, addr - mac_start, mac, 6);
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+ ret = true;
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+ break;
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+ case 3:
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+ ret |= ar93xx_wmac_otp_uncompress(base, addr, len, mac,
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+ mac_start, 6);
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ addr -= len + 2;
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+ }
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+
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+ iounmap(base);
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+ if (ret)
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+ memcpy(dest, mac, 6);
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+
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+ return ret;
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+}
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+
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void __init ath79_register_wmac(u8 *cal_data, u8 *mac_addr)
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{
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if (soc_is_ar913x())
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--- a/arch/mips/ath79/dev-wmac.h
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+++ b/arch/mips/ath79/dev-wmac.h
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@@ -14,5 +14,6 @@
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void ath79_register_wmac(u8 *cal_data, u8 *mac_addr);
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void ath79_register_wmac_simple(void);
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+bool ar93xx_wmac_read_mac_address(u8 *dest);
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#endif /* _ATH79_DEV_WMAC_H */
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--- a/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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+++ b/arch/mips/include/asm/mach-ath79/ar71xx_regs.h
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@@ -112,6 +112,14 @@
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#define QCA955X_EHCI1_BASE 0x1b400000
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#define QCA955X_EHCI_SIZE 0x1000
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+#define AR9300_OTP_BASE 0x14000
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+#define AR9300_OTP_STATUS 0x15f18
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+#define AR9300_OTP_STATUS_TYPE 0x7
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+#define AR9300_OTP_STATUS_VALID 0x4
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+#define AR9300_OTP_STATUS_ACCESS_BUSY 0x2
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+#define AR9300_OTP_STATUS_SM_BUSY 0x1
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+#define AR9300_OTP_READ_DATA 0x15f1c
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+
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/*
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* DDR_CTRL block
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*/
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@@ -149,6 +157,13 @@
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#define AR934X_DDR_REG_FLUSH_PCIE 0xa8
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#define AR934X_DDR_REG_FLUSH_WMAC 0xac
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+#define AR934X_OTP_BASE 0x30000
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+#define AR934X_OTP_STATUS 0x31018
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+#define AR934X_OTP_READ_DATA 0x3101c
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+#define AR934X_OTP_INTF2_ADDRESS 0x31008
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+#define AR934X_OTP_INTF3_ADDRESS 0x3100c
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+#define AR934X_OTP_PGENB_SETUP_HOLD_TIME_ADDRESS 0x31034
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+
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/*
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* PLL block
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*/
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