mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-22 23:12:32 +00:00
415 lines
9.8 KiB
Diff
415 lines
9.8 KiB
Diff
--- a/arch/arm/mach-cns3xxx/Makefile
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+++ b/arch/arm/mach-cns3xxx/Makefile
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@@ -1,3 +1,6 @@
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obj-$(CONFIG_ARCH_CNS3XXX) += core.o pm.o devices.o
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obj-$(CONFIG_PCI) += pcie.o
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obj-$(CONFIG_MACH_CNS3420VB) += cns3420vb.o
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+obj-$(CONFIG_SMP) += platsmp.o headsmp.o
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+obj-$(CONFIG_HOTPLUG_CPU) += hotplug.o
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+obj-$(CONFIG_LOCAL_TIMERS) += localtimer.o
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/headsmp.S
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@@ -0,0 +1,42 @@
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+/*
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+ * linux/arch/arm/mach-cns3xxx/headsmp.S
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+ *
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+ * Cloned from linux/arch/arm/plat-versatile/headsmp.S
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+ *
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+ * Copyright (c) 2003 ARM Limited
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+ * All Rights Reserved
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ */
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+#include <linux/linkage.h>
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+#include <linux/init.h>
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+
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+ __INIT
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+
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+/*
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+ * CNS3XXX specific entry point for secondary CPUs. This provides
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+ * a "holding pen" into which all secondary cores are held until we're
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+ * ready for them to initialise.
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+ */
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+ENTRY(cns3xxx_secondary_startup)
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+ mrc p15, 0, r0, c0, c0, 5
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+ and r0, r0, #15
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+ adr r4, 1f
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+ ldmia r4, {r5, r6}
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+ sub r4, r4, r5
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+ add r6, r6, r4
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+pen: ldr r7, [r6]
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+ cmp r7, r0
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+ bne pen
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+
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+ /*
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+ * we've been released from the holding pen: secondary_stack
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+ * should now contain the SVC stack for this core
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+ */
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+ b secondary_startup
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+
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+ .align
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+1: .long .
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+ .long pen_release
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/hotplug.c
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@@ -0,0 +1,130 @@
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+/* linux arch/arm/mach-cns3xxx/hotplug.c
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+ *
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+ * Cloned from linux/arch/arm/mach-realview/hotplug.c
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+ *
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+ * Copyright (C) 2002 ARM Ltd.
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+ * All Rights Reserved
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+*/
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+
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+#include <linux/kernel.h>
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+#include <linux/errno.h>
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+#include <linux/smp.h>
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+
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+#include <asm/cacheflush.h>
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+
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+extern volatile int pen_release;
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+
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+static inline void cpu_enter_lowpower(void)
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+{
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+ unsigned int v;
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+
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+ flush_cache_all();
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+ asm volatile(
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+ " mcr p15, 0, %1, c7, c5, 0\n"
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+ " mcr p15, 0, %1, c7, c10, 4\n"
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+ /*
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+ * Turn off coherency
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+ */
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+ " mrc p15, 0, %0, c1, c0, 1\n"
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+ " bic %0, %0, %3\n"
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+ " mcr p15, 0, %0, c1, c0, 1\n"
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+ " mrc p15, 0, %0, c1, c0, 0\n"
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+ " bic %0, %0, %2\n"
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+ " mcr p15, 0, %0, c1, c0, 0\n"
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+ : "=&r" (v)
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+ : "r" (0), "Ir" (CR_C), "Ir" (0x40)
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+ : "cc");
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+}
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+
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+static inline void cpu_leave_lowpower(void)
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+{
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+ unsigned int v;
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+
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+ asm volatile(
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+ "mrc p15, 0, %0, c1, c0, 0\n"
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+ " orr %0, %0, %1\n"
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+ " mcr p15, 0, %0, c1, c0, 0\n"
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+ " mrc p15, 0, %0, c1, c0, 1\n"
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+ " orr %0, %0, %2\n"
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+ " mcr p15, 0, %0, c1, c0, 1\n"
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+ : "=&r" (v)
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+ : "Ir" (CR_C), "Ir" (0x40)
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+ : "cc");
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+}
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+
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+static inline void platform_do_lowpower(unsigned int cpu, int *spurious)
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+{
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+ /*
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+ * there is no power-control hardware on this platform, so all
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+ * we can do is put the core into WFI; this is safe as the calling
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+ * code will have already disabled interrupts
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+ */
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+ for (;;) {
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+ /*
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+ * here's the WFI
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+ */
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+ asm(".word 0xe320f003\n"
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+ :
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+ :
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+ : "memory", "cc");
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+
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+ if (pen_release == cpu) {
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+ /*
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+ * OK, proper wakeup, we're done
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+ */
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+ break;
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+ }
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+
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+ /*
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+ * Getting here, means that we have come out of WFI without
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+ * having been woken up - this shouldn't happen
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+ *
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+ * Just note it happening - when we're woken, we can report
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+ * its occurrence.
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+ */
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+ (*spurious)++;
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+ }
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+}
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+
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+int platform_cpu_kill(unsigned int cpu)
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+{
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+ return 1;
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+}
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+
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+/*
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+ * platform-specific code to shutdown a CPU
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+ *
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+ * Called with IRQs disabled
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+ */
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+void platform_cpu_die(unsigned int cpu)
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+{
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+ int spurious = 0;
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+
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+ /*
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+ * we're ready for shutdown now, so do it
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+ */
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+ cpu_enter_lowpower();
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+ platform_do_lowpower(cpu, &spurious);
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+
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+ /*
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+ * bring this CPU back into the world of cache
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+ * coherency, and then restore interrupts
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+ */
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+ cpu_leave_lowpower();
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+
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+ if (spurious)
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+ pr_warn("CPU%u: %u spurious wakeup calls\n", cpu, spurious);
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+}
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+
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+int platform_cpu_disable(unsigned int cpu)
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+{
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+ /*
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+ * we don't allow CPU 0 to be shutdown (it is still too special
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+ * e.g. clock tick interrupts)
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+ */
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+ return cpu == 0 ? -EPERM : 0;
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+}
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--- a/arch/arm/mach-cns3xxx/Kconfig
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+++ b/arch/arm/mach-cns3xxx/Kconfig
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@@ -3,6 +3,7 @@ menu "CNS3XXX platform type"
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config MACH_CNS3420VB
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bool "Support for CNS3420 Validation Board"
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+ select HAVE_ARM_SCU if SMP
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select MIGHT_HAVE_PCI
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help
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Include support for the Cavium Networks CNS3420 MPCore Platform
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/localtimer.c
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@@ -0,0 +1,26 @@
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+/* linux/arch/arm/mach-cns3xxx/localtimer.c
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+ *
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+ * Cloned from linux/arch/arm/mach-realview/localtimer.c
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+ *
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+ * Copyright (C) 2002 ARM Ltd.
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+ * All Rights Reserved
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+*/
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+
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+#include <linux/clockchips.h>
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+
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+#include <asm/irq.h>
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+#include <asm/localtimer.h>
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+
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+/*
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+ * Setup the local clock events for a CPU.
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+ */
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+int __cpuinit local_timer_setup(struct clock_event_device *evt)
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+{
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+ evt->irq = IRQ_LOCALTIMER;
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+ twd_timer_setup(evt);
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+ return 0;
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+}
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--- /dev/null
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+++ b/arch/arm/mach-cns3xxx/platsmp.c
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@@ -0,0 +1,175 @@
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+/* linux/arch/arm/mach-cns3xxx/platsmp.c
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+ *
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+ * Copyright 2011 Gateworks Corporation
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+ * Chris Lang <clang@gateworks.com>
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+ *
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+ * Cloned from linux/arch/arm/mach-vexpress/platsmp.c
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+ *
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+ * Copyright (C) 2002 ARM Ltd.
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+ * All Rights Reserved
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+*/
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+
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+#include <linux/init.h>
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+#include <linux/errno.h>
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+#include <linux/delay.h>
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+#include <linux/device.h>
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+#include <linux/jiffies.h>
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+#include <linux/smp.h>
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+#include <linux/io.h>
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+
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+#include <asm/cacheflush.h>
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+#include <asm/hardware/gic.h>
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+#include <asm/smp_scu.h>
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+#include <asm/unified.h>
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+
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+#include <mach/cns3xxx.h>
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+
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+extern void cns3xxx_secondary_startup(void);
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+
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+/*
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+ * control for which core is the next to come out of the secondary
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+ * boot "holding pen"
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+ */
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+
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+volatile int __cpuinitdata pen_release = -1;
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+
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+/*
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+ * Write pen_release in a way that is guaranteed to be visible to all
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+ * observers, irrespective of whether they're taking part in coherency
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+ * or not. This is necessary for the hotplug code to work reliably.
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+ */
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+static void write_pen_release(int val)
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+{
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+ pen_release = val;
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+ smp_wmb();
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+ __cpuc_flush_dcache_area((void *)&pen_release, sizeof(pen_release));
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+ outer_clean_range(__pa(&pen_release), __pa(&pen_release + 1));
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+}
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+
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+static void __iomem *scu_base_addr(void)
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+{
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+ return (void __iomem *)(CNS3XXX_TC11MP_SCU_BASE_VIRT);
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+}
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+
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+static DEFINE_SPINLOCK(boot_lock);
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+
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+void __cpuinit platform_secondary_init(unsigned int cpu)
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+{
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+ /*
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+ * if any interrupts are already enabled for the primary
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+ * core (e.g. timer irq), then they will not have been enabled
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+ * for us: do so
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+ */
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+ gic_secondary_init(0);
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+
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+ /*
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+ * let the primary processor know we're out of the
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+ * pen, then head off into the C entry point
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+ */
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+ write_pen_release(-1);
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+
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+ /*
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+ * Synchronise with the boot thread.
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+ */
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+ spin_lock(&boot_lock);
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+ spin_unlock(&boot_lock);
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+}
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+
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+int __cpuinit boot_secondary(unsigned int cpu, struct task_struct *idle)
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+{
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+ unsigned long timeout;
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+
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+ /*
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+ * Set synchronisation state between this boot processor
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+ * and the secondary one
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+ */
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+ spin_lock(&boot_lock);
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+
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+ /*
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+ * The secondary processor is waiting to be released from
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+ * the holding pen - release it, then wait for it to flag
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+ * that it has been released by resetting pen_release.
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+ *
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+ * Note that "pen_release" is the hardware CPU ID, whereas
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+ * "cpu" is Linux's internal ID.
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+ */
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+ write_pen_release(cpu);
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+
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+ /*
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+ * Send the secondary CPU a soft interrupt, thereby causing
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+ * the boot monitor to read the system wide flags register,
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+ * and branch to the address found there.
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+ */
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+ gic_raise_softirq(cpumask_of(cpu), 1);
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+
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+ timeout = jiffies + (1 * HZ);
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+ while (time_before(jiffies, timeout)) {
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+ smp_rmb();
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+ if (pen_release == -1)
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+ break;
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+
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+ udelay(10);
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+ }
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+
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+ /*
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+ * now the secondary core is starting up let it run its
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+ * calibrations, then wait for it to finish
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+ */
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+ spin_unlock(&boot_lock);
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+
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+ return pen_release != -1 ? -ENOSYS : 0;
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+}
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+
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+/*
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+ * Initialise the CPU possible map early - this describes the CPUs
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+ * which may be present or become present in the system.
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+ */
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+
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+void __init smp_init_cpus(void)
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+{
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+ void __iomem *scu_base = scu_base_addr();
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+ unsigned int i, ncores;
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+
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+ ncores = scu_base ? scu_get_core_count(scu_base) : 1;
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+
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+ /* sanity check */
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+ if (ncores > NR_CPUS) {
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+ printk(KERN_WARNING
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+ "cns3xxx: no. of cores (%d) greater than configured "
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+ "maximum of %d - clipping\n",
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+ ncores, NR_CPUS);
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+ ncores = NR_CPUS;
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+ }
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+
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+ for (i = 0; i < ncores; i++)
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+ set_cpu_possible(i, true);
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+
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+ set_smp_cross_call(gic_raise_softirq);
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+}
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+
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+void __init platform_smp_prepare_cpus(unsigned int max_cpus)
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+{
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+ int i;
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+
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+ /*
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+ * Initialise the present map, which describes the set of CPUs
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+ * actually populated at the present time.
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+ */
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+ for (i = 0; i < max_cpus; i++)
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+ set_cpu_present(i, true);
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+
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+ scu_enable(scu_base_addr());
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+
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+ /*
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+ * Write the address of secondary startup into the
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+ * system-wide flags register. The boot monitor waits
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+ * until it receives a soft interrupt, and then the
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+ * secondary CPU branches to this address.
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+ */
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+ __raw_writel(virt_to_phys(cns3xxx_secondary_startup),
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+ (void __iomem *)(CNS3XXX_MISC_BASE_VIRT + 0x0600));
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+}
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--- a/arch/arm/Kconfig
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+++ b/arch/arm/Kconfig
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@@ -373,6 +373,7 @@ config ARCH_CNS3XXX
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select MIGHT_HAVE_PCI
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select PCI_DOMAINS if PCI
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select HAVE_ARM_TWD
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+ select HAVE_SMP
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help
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Support for Cavium Networks CNS3XXX platform.
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