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230 lines
8.4 KiB
C
230 lines
8.4 KiB
C
// SPDX-License-Identifier: (GPL-2.0)
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/*
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* oxnas SoC reset driver
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* based on:
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* Microsemi MIPS SoC reset driver
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* and ox820_assert_system_reset() written by Ma Hajun <mahaijuns@gmail.com>
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*
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* License: GPL
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* Copyright (c) 2013 Ma Hajun <mahaijuns@gmail.com>
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* Copyright (c) 2017 Microsemi Corporation
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* Copyright (c) 2019 Daniel Golle <daniel@makrotopia.org>
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*/
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#include <linux/delay.h>
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#include <linux/io.h>
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#include <linux/notifier.h>
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#include <linux/mfd/syscon.h>
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#include <linux/of_address.h>
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#include <linux/of_device.h>
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#include <linux/platform_device.h>
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#include <linux/reboot.h>
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#include <linux/regmap.h>
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/* bit numbers of reset control register */
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#define OX820_SYS_CTRL_RST_SCU 0
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#define OX820_SYS_CTRL_RST_COPRO 1
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#define OX820_SYS_CTRL_RST_ARM0 2
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#define OX820_SYS_CTRL_RST_ARM1 3
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#define OX820_SYS_CTRL_RST_USBHS 4
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#define OX820_SYS_CTRL_RST_USBHSPHYA 5
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#define OX820_SYS_CTRL_RST_MACA 6
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#define OX820_SYS_CTRL_RST_MAC OX820_SYS_CTRL_RST_MACA
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#define OX820_SYS_CTRL_RST_PCIEA 7
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#define OX820_SYS_CTRL_RST_SGDMA 8
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#define OX820_SYS_CTRL_RST_CIPHER 9
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#define OX820_SYS_CTRL_RST_DDR 10
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#define OX820_SYS_CTRL_RST_SATA 11
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#define OX820_SYS_CTRL_RST_SATA_LINK 12
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#define OX820_SYS_CTRL_RST_SATA_PHY 13
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#define OX820_SYS_CTRL_RST_PCIEPHY 14
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#define OX820_SYS_CTRL_RST_STATIC 15
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#define OX820_SYS_CTRL_RST_GPIO 16
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#define OX820_SYS_CTRL_RST_UART1 17
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#define OX820_SYS_CTRL_RST_UART2 18
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#define OX820_SYS_CTRL_RST_MISC 19
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#define OX820_SYS_CTRL_RST_I2S 20
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#define OX820_SYS_CTRL_RST_SD 21
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#define OX820_SYS_CTRL_RST_MACB 22
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#define OX820_SYS_CTRL_RST_PCIEB 23
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#define OX820_SYS_CTRL_RST_VIDEO 24
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#define OX820_SYS_CTRL_RST_DDR_PHY 25
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#define OX820_SYS_CTRL_RST_USBHSPHYB 26
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#define OX820_SYS_CTRL_RST_USBDEV 27
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#define OX820_SYS_CTRL_RST_ARMDBG 29
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#define OX820_SYS_CTRL_RST_PLLA 30
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#define OX820_SYS_CTRL_RST_PLLB 31
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/* bit numbers of clock control register */
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#define OX820_SYS_CTRL_CLK_COPRO 0
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#define OX820_SYS_CTRL_CLK_DMA 1
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#define OX820_SYS_CTRL_CLK_CIPHER 2
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#define OX820_SYS_CTRL_CLK_SD 3
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#define OX820_SYS_CTRL_CLK_SATA 4
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#define OX820_SYS_CTRL_CLK_I2S 5
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#define OX820_SYS_CTRL_CLK_USBHS 6
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#define OX820_SYS_CTRL_CLK_MACA 7
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#define OX820_SYS_CTRL_CLK_MAC OX820_SYS_CTRL_CLK_MACA
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#define OX820_SYS_CTRL_CLK_PCIEA 8
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#define OX820_SYS_CTRL_CLK_STATIC 9
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#define OX820_SYS_CTRL_CLK_MACB 10
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#define OX820_SYS_CTRL_CLK_PCIEB 11
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#define OX820_SYS_CTRL_CLK_REF600 12
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#define OX820_SYS_CTRL_CLK_USBDEV 13
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#define OX820_SYS_CTRL_CLK_DDR 14
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#define OX820_SYS_CTRL_CLK_DDRPHY 15
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#define OX820_SYS_CTRL_CLK_DDRCK 16
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/* Regmap offsets */
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#define OX820_CLK_SET_REGOFFSET 0x2c
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#define OX820_CLK_CLR_REGOFFSET 0x30
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#define OX820_RST_SET_REGOFFSET 0x34
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#define OX820_RST_CLR_REGOFFSET 0x38
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#define OX820_SECONDARY_SEL_REGOFFSET 0x14
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#define OX820_TERTIARY_SEL_REGOFFSET 0x8c
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#define OX820_QUATERNARY_SEL_REGOFFSET 0x94
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#define OX820_DEBUG_SEL_REGOFFSET 0x9c
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#define OX820_ALTERNATIVE_SEL_REGOFFSET 0xa4
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#define OX820_PULLUP_SEL_REGOFFSET 0xac
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#define OX820_SEC_SECONDARY_SEL_REGOFFSET 0x100014
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#define OX820_SEC_TERTIARY_SEL_REGOFFSET 0x10008c
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#define OX820_SEC_QUATERNARY_SEL_REGOFFSET 0x100094
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#define OX820_SEC_DEBUG_SEL_REGOFFSET 0x10009c
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#define OX820_SEC_ALTERNATIVE_SEL_REGOFFSET 0x1000a4
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#define OX820_SEC_PULLUP_SEL_REGOFFSET 0x1000ac
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struct oxnas_restart_context {
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struct regmap *sys_ctrl;
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struct notifier_block restart_handler;
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};
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static int ox820_restart_handle(struct notifier_block *this,
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unsigned long mode, void *cmd)
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{
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struct oxnas_restart_context *ctx = container_of(this, struct
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oxnas_restart_context,
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restart_handler);
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u32 value;
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/* Assert reset to cores as per power on defaults
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* Don't touch the DDR interface as things will come to an impromptu stop
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* NB Possibly should be asserting reset for PLLB, but there are timing
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* concerns here according to the docs */
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value = BIT(OX820_SYS_CTRL_RST_COPRO) |
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BIT(OX820_SYS_CTRL_RST_USBHS) |
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BIT(OX820_SYS_CTRL_RST_USBHSPHYA) |
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BIT(OX820_SYS_CTRL_RST_MACA) |
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BIT(OX820_SYS_CTRL_RST_PCIEA) |
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BIT(OX820_SYS_CTRL_RST_SGDMA) |
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BIT(OX820_SYS_CTRL_RST_CIPHER) |
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BIT(OX820_SYS_CTRL_RST_SATA) |
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BIT(OX820_SYS_CTRL_RST_SATA_LINK) |
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BIT(OX820_SYS_CTRL_RST_SATA_PHY) |
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BIT(OX820_SYS_CTRL_RST_PCIEPHY) |
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BIT(OX820_SYS_CTRL_RST_STATIC) |
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BIT(OX820_SYS_CTRL_RST_UART1) |
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BIT(OX820_SYS_CTRL_RST_UART2) |
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BIT(OX820_SYS_CTRL_RST_MISC) |
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BIT(OX820_SYS_CTRL_RST_I2S) |
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BIT(OX820_SYS_CTRL_RST_SD) |
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BIT(OX820_SYS_CTRL_RST_MACB) |
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BIT(OX820_SYS_CTRL_RST_PCIEB) |
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BIT(OX820_SYS_CTRL_RST_VIDEO) |
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BIT(OX820_SYS_CTRL_RST_USBHSPHYB) |
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BIT(OX820_SYS_CTRL_RST_USBDEV);
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regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
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/* Release reset to cores as per power on defaults */
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regmap_write(ctx->sys_ctrl, OX820_RST_CLR_REGOFFSET, BIT(OX820_SYS_CTRL_RST_GPIO));
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/* Disable clocks to cores as per power-on defaults - must leave DDR
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* related clocks enabled otherwise we'll stop rather abruptly. */
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value =
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BIT(OX820_SYS_CTRL_CLK_COPRO) |
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BIT(OX820_SYS_CTRL_CLK_DMA) |
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BIT(OX820_SYS_CTRL_CLK_CIPHER) |
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BIT(OX820_SYS_CTRL_CLK_SD) |
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BIT(OX820_SYS_CTRL_CLK_SATA) |
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BIT(OX820_SYS_CTRL_CLK_I2S) |
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BIT(OX820_SYS_CTRL_CLK_USBHS) |
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BIT(OX820_SYS_CTRL_CLK_MAC) |
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BIT(OX820_SYS_CTRL_CLK_PCIEA) |
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BIT(OX820_SYS_CTRL_CLK_STATIC) |
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BIT(OX820_SYS_CTRL_CLK_MACB) |
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BIT(OX820_SYS_CTRL_CLK_PCIEB) |
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BIT(OX820_SYS_CTRL_CLK_REF600) |
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BIT(OX820_SYS_CTRL_CLK_USBDEV);
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regmap_write(ctx->sys_ctrl, OX820_CLK_CLR_REGOFFSET, value);
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/* Enable clocks to cores as per power-on defaults */
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/* Set sys-control pin mux'ing as per power-on defaults */
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regmap_write(ctx->sys_ctrl, OX820_SECONDARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_TERTIARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_QUATERNARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_DEBUG_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_ALTERNATIVE_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_PULLUP_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_SECONDARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_TERTIARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_QUATERNARY_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_DEBUG_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_ALTERNATIVE_SEL_REGOFFSET, 0);
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regmap_write(ctx->sys_ctrl, OX820_SEC_PULLUP_SEL_REGOFFSET, 0);
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/* No need to save any state, as the ROM loader can determine whether
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* reset is due to power cycling or programatic action, just hit the
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* (self-clearing) CPU reset bit of the block reset register */
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value =
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BIT(OX820_SYS_CTRL_RST_SCU) |
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BIT(OX820_SYS_CTRL_RST_ARM0) |
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BIT(OX820_SYS_CTRL_RST_ARM1);
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regmap_write(ctx->sys_ctrl, OX820_RST_SET_REGOFFSET, value);
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pr_emerg("Unable to restart system\n");
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return NOTIFY_DONE;
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}
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static int ox820_restart_probe(struct platform_device *pdev)
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{
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struct oxnas_restart_context *ctx;
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struct regmap *sys_ctrl;
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struct device *dev = &pdev->dev;
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int err = 0;
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sys_ctrl = syscon_node_to_regmap(pdev->dev.of_node);
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if (IS_ERR(sys_ctrl))
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return PTR_ERR(sys_ctrl);
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ctx = devm_kzalloc(&pdev->dev, sizeof(*ctx), GFP_KERNEL);
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if (!ctx)
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return -ENOMEM;
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ctx->sys_ctrl = sys_ctrl;
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ctx->restart_handler.notifier_call = ox820_restart_handle;
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ctx->restart_handler.priority = 192;
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err = register_restart_handler(&ctx->restart_handler);
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if (err)
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dev_err(dev, "can't register restart notifier (err=%d)\n", err);
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return err;
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}
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static const struct of_device_id ox820_restart_of_match[] = {
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{ .compatible = "oxsemi,ox820-sys-ctrl" },
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{}
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};
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static struct platform_driver ox820_restart_driver = {
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.probe = ox820_restart_probe,
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.driver = {
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.name = "ox820-chip-reset",
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.of_match_table = ox820_restart_of_match,
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},
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};
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builtin_platform_driver(ox820_restart_driver);
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