mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-20 14:13:16 +00:00
6bf179b270
Switch to the mainline Lantiq PCIe PHY driver and update the vr9.dtsi
accordingly.
The Lantiq IRQ SMP support added upstream required changes to the SoC
dtsi as well.
Following changes are made to the Lantiq kernel patches:
0005-lantiq_etop-pass-struct-device-to-DMA-API-functions.patch
0006-MIPS-lantiq-pass-struct-device-to-DMA-API-functions.patch
applied upstream
0008-MIPS-lantiq-backport-old-timer-code.patch
access_ok API update because it lost it's type (which was the first)
parameter in upstream commit 96d4f267e40f95 ("Remove 'type' argument
from access_ok() function")
0024-MIPS-lantiq-autoselect-soc-rev-matching-fw.patch
merged into 0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
revert upstream changes required for upstream xrx200 ethernet and
xrx200 (DSA) switch driver but breaking our driver
0026-MIPS-lantiq-Add-GPHY-Firmware-loader.patch
required for our driver but dropped upstream, add former upstream
version
0028-NET-lantiq-various-etop-fixes.patch
now has to use the phy_set_max_speed API instead of modifying
phydev->supported. Also call ltq_dma_enable_irq() in
ltq_etop_open() based on upstream commit cc973aecf0b054 ("MIPS:
lantiq: Do not enable IRQs in dma open")
Signed-off-by: Mathias Kresin <dev@kresin.me>
Signed-off-by: Martin Blumenstingl <martin.blumenstingl@googlemail.com>
295 lines
10 KiB
Diff
295 lines
10 KiB
Diff
From 0a63ab263725c427051a8bbaa0732b749627da27 Mon Sep 17 00:00:00 2001
|
|
From: John Crispin <blogic@openwrt.org>
|
|
Date: Thu, 7 Aug 2014 18:15:36 +0200
|
|
Subject: [PATCH 23/36] NET: PHY: adds driver for lantiq PHY11G
|
|
|
|
Signed-off-by: John Crispin <blogic@openwrt.org>
|
|
---
|
|
drivers/net/phy/Kconfig | 5 +
|
|
drivers/net/phy/Makefile | 1 +
|
|
drivers/net/phy/lantiq.c | 231 ++++++++++++++++++++++++++++++++++++++++++++++
|
|
3 files changed, 237 insertions(+)
|
|
create mode 100644 drivers/net/phy/lantiq.c
|
|
|
|
--- a/drivers/net/phy/intel-xway.c
|
|
+++ b/drivers/net/phy/intel-xway.c
|
|
@@ -145,6 +145,51 @@
|
|
#define PHY_ID_PHY11G_VR9_1_2 0xD565A409
|
|
#define PHY_ID_PHY22F_VR9_1_2 0xD565A419
|
|
|
|
+#if IS_ENABLED(CONFIG_OF_MDIO)
|
|
+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
|
|
+{
|
|
+ u32 tmp;
|
|
+
|
|
+ /* store the led values if one was passed by the devicetree */
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledch", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCH, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,ledcl", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LEDCL, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0h", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0H, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led0l", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED0L, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1h", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1H, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led1l", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED1L, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2h", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led2l", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3h", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3H, tmp);
|
|
+
|
|
+ if (!of_property_read_u32(phydev->mdio.dev.of_node, "lantiq,led3l", &tmp))
|
|
+ phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED3L, tmp);
|
|
+
|
|
+ return 0;
|
|
+}
|
|
+#else
|
|
+static int vr9_gphy_of_reg_init(struct phy_device *phydev)
|
|
+{
|
|
+ return 0;
|
|
+}
|
|
+#endif /* CONFIG_OF_MDIO */
|
|
+
|
|
static int xway_gphy_config_init(struct phy_device *phydev)
|
|
{
|
|
int err;
|
|
@@ -183,6 +228,7 @@ static int xway_gphy_config_init(struct
|
|
phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2H, ledxh);
|
|
phy_write_mmd(phydev, MDIO_MMD_VEND2, XWAY_MMD_LED2L, ledxl);
|
|
|
|
+ vr9_gphy_of_reg_init(phydev);
|
|
return 0;
|
|
}
|
|
|
|
--- /dev/null
|
|
+++ b/Documentation/devicetree/bindings/phy/phy-lanitq.txt
|
|
@@ -0,0 +1,216 @@
|
|
+Lanitq PHY binding
|
|
+============================================
|
|
+
|
|
+This devicetree binding controls the lantiq ethernet phys led functionality.
|
|
+
|
|
+Example:
|
|
+ mdio@0 {
|
|
+ #address-cells = <1>;
|
|
+ #size-cells = <0>;
|
|
+ compatible = "lantiq,xrx200-mdio";
|
|
+ phy5: ethernet-phy@5 {
|
|
+ reg = <0x1>;
|
|
+ compatible = "lantiq,phy11g", "ethernet-phy-ieee802.3-c22";
|
|
+ };
|
|
+ phy11: ethernet-phy@11 {
|
|
+ reg = <0x11>;
|
|
+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
|
+ lantiq,led2h = <0x00>;
|
|
+ lantiq,led2l = <0x03>;
|
|
+ };
|
|
+ phy12: ethernet-phy@12 {
|
|
+ reg = <0x12>;
|
|
+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
|
+ lantiq,led1h = <0x00>;
|
|
+ lantiq,led1l = <0x03>;
|
|
+ };
|
|
+ phy13: ethernet-phy@13 {
|
|
+ reg = <0x13>;
|
|
+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
|
+ lantiq,led2h = <0x00>;
|
|
+ lantiq,led2l = <0x03>;
|
|
+ };
|
|
+ phy14: ethernet-phy@14 {
|
|
+ reg = <0x14>;
|
|
+ compatible = "lantiq,phy22f", "ethernet-phy-ieee802.3-c22";
|
|
+ lantiq,led1h = <0x00>;
|
|
+ lantiq,led1l = <0x03>;
|
|
+ };
|
|
+ };
|
|
+
|
|
+Register Description
|
|
+============================================
|
|
+
|
|
+LEDCH:
|
|
+
|
|
+Name Hardware Reset Value
|
|
+LEDCH 0x00C5
|
|
+
|
|
+| 15 | | | | | | | 8 |
|
|
+=========================================
|
|
+| RES |
|
|
+=========================================
|
|
+
|
|
+| 7 | | | | | | | 0 |
|
|
+=========================================
|
|
+| FBF | SBF |RES | NACS |
|
|
+=========================================
|
|
+
|
|
+Field Bits Type Description
|
|
+FBF 7:6 RW Fast Blink Frequency
|
|
+ ---
|
|
+ 0x0 (00b) F02HZ 2 Hz blinking frequency
|
|
+ 0x1 (01b) F04HZ 4 Hz blinking frequency
|
|
+ 0x2 (10b) F08HZ 8 Hz blinking frequency
|
|
+ 0x3 (11b) F16HZ 16 Hz blinking frequency
|
|
+
|
|
+SBF 5:4 RW Slow Blink Frequency
|
|
+ ---
|
|
+ 0x0 (00b) F02HZ 2 Hz blinking frequency
|
|
+ 0x1 (01b) F04HZ 4 Hz blinking frequency
|
|
+ 0x2 (10b) F08HZ 8 Hz blinking frequency
|
|
+ 0x3 (11b) F16HZ 16 Hz blinking frequency
|
|
+
|
|
+NACS 2:0 RW Inverse of Scan Function
|
|
+ ---
|
|
+ 0x0 (000b) NONE No Function
|
|
+ 0x1 (001b) LINK Complex function enabled when link is up
|
|
+ 0x2 (010b) PDOWN Complex function enabled when device is powered-down
|
|
+ 0x3 (011b) EEE Complex function enabled when device is in EEE mode
|
|
+ 0x4 (100b) ANEG Complex function enabled when auto-negotiation is running
|
|
+ 0x5 (101b) ABIST Complex function enabled when analog self-test is running
|
|
+ 0x6 (110b) CDIAG Complex function enabled when cable diagnostics are running
|
|
+ 0x7 (111b) TEST Complex function enabled when test mode is running
|
|
+
|
|
+LEDCL:
|
|
+
|
|
+Name Hardware Reset Value
|
|
+LEDCL 0x0067
|
|
+
|
|
+| 15 | | | | | | | 8 |
|
|
+=========================================
|
|
+| RES |
|
|
+=========================================
|
|
+
|
|
+| 7 | | | | | | | 0 |
|
|
+=========================================
|
|
+|RES | SCAN |RES | CBLINK |
|
|
+=========================================
|
|
+
|
|
+Field Bits Type Description
|
|
+SCAN 6:4 RW Complex Scan Configuration
|
|
+ ---
|
|
+ 000 B NONE No Function
|
|
+ 001 B LINK Complex function enabled when link is up
|
|
+ 010 B PDOWN Complex function enabled when device is powered-down
|
|
+ 011 B EEE Complex function enabled when device is in EEE mode
|
|
+ 100 B ANEG Complex function enabled when auto-negotiation is running
|
|
+ 101 B ABIST Complex function enabled when analog self-test is running
|
|
+ 110 B CDIAG Complex function enabled when cable diagnostics are running
|
|
+ 111 B TEST Complex function enabled when test mode is running
|
|
+
|
|
+CBLINK 2:0 RW Complex Blinking Configuration
|
|
+ ---
|
|
+ 000 B NONE No Function
|
|
+ 001 B LINK Complex function enabled when link is up
|
|
+ 010 B PDOWN Complex function enabled when device is powered-down
|
|
+ 011 B EEE Complex function enabled when device is in EEE mode
|
|
+ 100 B ANEG Complex function enabled when auto-negotiation is running
|
|
+ 101 B ABIST Complex function enabled when analog self-test is running
|
|
+ 110 B CDIAG Complex function enabled when cable diagnostics are running
|
|
+ 111 B TEST Complex function enabled when test mode is running
|
|
+
|
|
+LEDxH:
|
|
+
|
|
+Name Hardware Reset Value
|
|
+LED0H 0x0070
|
|
+LED1H 0x0020
|
|
+LED2H 0x0040
|
|
+LED3H 0x0040
|
|
+
|
|
+| 15 | | | | | | | 8 |
|
|
+=========================================
|
|
+| RES |
|
|
+=========================================
|
|
+
|
|
+| 7 | | | | | | | 0 |
|
|
+=========================================
|
|
+| CON | BLINKF |
|
|
+=========================================
|
|
+
|
|
+Field Bits Type Description
|
|
+CON 7:4 RW Constant On Configuration
|
|
+ ---
|
|
+ 0x0 (0000b) NONE LED does not light up constantly
|
|
+ 0x1 (0001b) LINK10 LED is on when link is 10 Mbit/s
|
|
+ 0x2 (0010b) LINK100 LED is on when link is 100 Mbit/s
|
|
+ 0x3 (0011b) LINK10X LED is on when link is 10/100 Mbit/s
|
|
+ 0x4 (0100b) LINK1000 LED is on when link is 1000 Mbit/s
|
|
+ 0x5 (0101b) LINK10_0 LED is on when link is 10/1000 Mbit/s
|
|
+ 0x6 (0110b) LINK100X LED is on when link is 100/1000 Mbit/s
|
|
+ 0x7 (0111b) LINK10XX LED is on when link is 10/100/1000 Mbit/s
|
|
+ 0x8 (1000b) PDOWN LED is on when device is powered-down
|
|
+ 0x9 (1001b) EEE LED is on when device is in EEE mode
|
|
+ 0xA (1010b) ANEG LED is on when auto-negotiation is running
|
|
+ 0xB (1011b) ABIST LED is on when analog self-test is running
|
|
+ 0xC (1100b) CDIAG LED is on when cable diagnostics are running
|
|
+
|
|
+BLINKF 3:0 RW Fast Blinking Configuration
|
|
+ ---
|
|
+ 0x0 (0000b) NONE No Blinking
|
|
+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
|
|
+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
|
|
+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
|
|
+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
|
|
+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
|
|
+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
|
|
+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
|
|
+ 0x8 (1000b) PDOWN Blink when device is powered-down
|
|
+ 0x9 (1001b) EEE Blink when device is in EEE mode
|
|
+ 0xA (1010b) ANEG Blink when auto-negotiation is running
|
|
+ 0xB (1011b) ABIST Blink when analog self-test is running
|
|
+ 0xC (1100b) CDIAG Blink when cable diagnostics are running
|
|
+
|
|
+LEDxL:
|
|
+
|
|
+Name Hardware Reset Value
|
|
+LED0L 0x0003
|
|
+LED1L 0x0000
|
|
+LED2L 0x0000
|
|
+LED3L 0x0020
|
|
+
|
|
+| 15 | | | | | | | 8 |
|
|
+=========================================
|
|
+| RES |
|
|
+=========================================
|
|
+
|
|
+| 7 | | | | | | | 0 |
|
|
+=========================================
|
|
+| BLINKS | PULSE |
|
|
+=========================================
|
|
+
|
|
+Field Bits Type Description
|
|
+BLINKS 7:4 RW Slow Blinkin Configuration
|
|
+ ---
|
|
+ 0x0 (0000b) NONE No Blinking
|
|
+ 0x1 (0001b) LINK10 Blink when link is 10 Mbit/s
|
|
+ 0x2 (0010b) LINK100 Blink when link is 100 Mbit/s
|
|
+ 0x3 (0011b) LINK10X Blink when link is 10/100 Mbit/s
|
|
+ 0x4 (0100b) LINK1000 Blink when link is 1000 Mbit/s
|
|
+ 0x5 (0101b) LINK10_0 Blink when link is 10/1000 Mbit/s
|
|
+ 0x6 (0110b) LINK100X Blink when link is 100/1000 Mbit/s
|
|
+ 0x7 (0111b) LINK10XX Blink when link is 10/100/1000 Mbit/s
|
|
+ 0x8 (1000b) PDOWN Blink when device is powered-down
|
|
+ 0x9 (1001b) EEE Blink when device is in EEE mode
|
|
+ 0xA (1010b) ANEG Blink when auto-negotiation is running
|
|
+ 0xB (1011b) ABIST Blink when analog self-test is running
|
|
+ 0xC (1100b) CDIAG Blink when cable diagnostics are runningning
|
|
+
|
|
+PULSE 3:0 RW Pulsing Configuration
|
|
+ The pulse field is a mask field by which certain events can be combined
|
|
+ ---
|
|
+ 0x0 (0000b) NONE No pulsing
|
|
+ 0x1 (0001b) TXACT Transmit activity
|
|
+ 0x2 (0010b) RXACT Receive activity
|
|
+ 0x4 (0100b) COL Collision
|
|
+ 0x8 (1000b) RES Reserved
|