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cef420e8f7
Rather than having separate patches for each GSBI node added, this patch consolidates the existing GSBI1 patch into 083-ipq8064-dtsi-additions.patch. In addition, GSBI6 and GSBI7 I2C nodes, required for the MR42 and MR52 respectively, are added. Signed-off-by: Matthew Hagan <mnhagan88@gmail.com>
47 lines
1.9 KiB
Diff
47 lines
1.9 KiB
Diff
From 84909e85881d67244240c9f40974ce12a51e3886 Mon Sep 17 00:00:00 2001
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From: Ansuel Smith <ansuelsmth@gmail.com>
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Date: Tue, 11 May 2021 23:09:45 +0200
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Subject: [PATCH] ARM: dts: qcom: reduce pci IO size to 64K
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The current value is probably a typo and is actually uncommon to find
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1MB IO space even on a x86 arch. Also with recent changes to the pci
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driver, pci1 and pci2 now fails to function as any connected device
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fails any reg read/write. Reduce this to 64K as it should be more than
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enough and 3 * 64K of total IO space doesn't exceed the IO_SPACE_LIMIT
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hardcoded for the ARM arch.
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Signed-off-by: Ansuel Smith <ansuelsmth@gmail.com>
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---
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arch/arm/boot/dts/qcom-ipq8064.dtsi | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/arch/arm/boot/dts/qcom-ipq8064.dtsi
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+++ b/arch/arm/boot/dts/qcom-ipq8064.dtsi
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@@ -1163,7 +1163,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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- ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x0fe00000 0x0fe00000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x08000000 0x08000000 0 0x07e00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1214,7 +1214,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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- ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x31e00000 0x31e00000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x2e000000 0x2e000000 0 0x03e00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 57 IRQ_TYPE_LEVEL_HIGH>;
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@@ -1265,7 +1265,7 @@
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#address-cells = <3>;
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#size-cells = <2>;
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- ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00100000 /* downstream I/O */
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+ ranges = <0x81000000 0 0x35e00000 0x35e00000 0 0x00010000 /* downstream I/O */
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0x82000000 0 0x32000000 0x32000000 0 0x03e00000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>;
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