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6b4fcc55a9
Add patch fixing support for MMC. Additional clock are needed for MMC to work and some small fixup to make the Mediatek MMC driver on Airoha SoC. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com> (cherry picked from commit be5a9ff24b9c3b7d1b5bf508b84a35be9f9b3ea9)
83 lines
2.5 KiB
Diff
83 lines
2.5 KiB
Diff
From 04cd09990fdc3106d9fc4c47dda100e521d62a43 Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 18 Dec 2024 10:03:45 +0100
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Subject: [PATCH 1/4] clk: en7523: Rework clock handling for different clock
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numbers
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Airoha EN7581 SoC have additional clock compared to EN7523 but current
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driver permits to only support up to EN7523 clock numbers.
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To handle this, rework the clock handling and permit to declare the
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clocks number in match_data and alloca clk_data based on the compatible
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match_data.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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drivers/clk/clk-en7523.c | 14 ++++++++------
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1 file changed, 8 insertions(+), 6 deletions(-)
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--- a/drivers/clk/clk-en7523.c
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+++ b/drivers/clk/clk-en7523.c
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@@ -75,6 +75,7 @@ struct en_rst_data {
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};
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struct en_clk_soc_data {
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+ u32 num_clocks;
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const struct clk_ops pcie_ops;
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int (*hw_init)(struct platform_device *pdev,
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struct clk_hw_onecell_data *clk_data);
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@@ -525,8 +526,6 @@ static void en7523_register_clocks(struc
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hw = en7523_register_pcie_clk(dev, np_base);
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clk_data->hws[EN7523_CLK_PCIE] = hw;
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-
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- clk_data->num = EN7523_NUM_CLOCKS;
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}
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static int en7523_clk_hw_init(struct platform_device *pdev,
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@@ -587,8 +586,6 @@ static void en7581_register_clocks(struc
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hw = en7523_register_pcie_clk(dev, base);
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clk_data->hws[EN7523_CLK_PCIE] = hw;
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-
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- clk_data->num = EN7523_NUM_CLOCKS;
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}
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static int en7523_reset_update(struct reset_controller_dev *rcdev,
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@@ -702,21 +699,24 @@ static int en7523_clk_probe(struct platf
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struct clk_hw_onecell_data *clk_data;
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int r;
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+ soc_data = device_get_match_data(&pdev->dev);
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+
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clk_data = devm_kzalloc(&pdev->dev,
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- struct_size(clk_data, hws, EN7523_NUM_CLOCKS),
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+ struct_size(clk_data, hws, soc_data->num_clocks),
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GFP_KERNEL);
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if (!clk_data)
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return -ENOMEM;
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- soc_data = device_get_match_data(&pdev->dev);
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r = soc_data->hw_init(pdev, clk_data);
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if (r)
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return r;
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+ clk_data->num = soc_data->num_clocks;
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return of_clk_add_hw_provider(node, of_clk_hw_onecell_get, clk_data);
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}
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static const struct en_clk_soc_data en7523_data = {
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+ .num_clocks = ARRAY_SIZE(en7523_base_clks) + 1,
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.pcie_ops = {
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.is_enabled = en7523_pci_is_enabled,
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.prepare = en7523_pci_prepare,
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@@ -726,6 +726,8 @@ static const struct en_clk_soc_data en75
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};
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static const struct en_clk_soc_data en7581_data = {
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+ /* We increment num_clocks by 1 to account for additional PCIe clock */
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+ .num_clocks = ARRAY_SIZE(en7581_base_clks) + 1,
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.pcie_ops = {
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.is_enabled = en7581_pci_is_enabled,
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.enable = en7581_pci_enable,
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