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63a0a4d85b
This adds support for the RTL9300 and RTL9310 I2C controller. The controller implements the SMBus protocol for SMBus transfers over an I2C bus. The driver supports selecting one of the 2 possible SCL pins and any of the 8 possible SDA pins. Bus speeds of 100kHz (standard speed) and 400kHz (high speed I2C) are supported. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
63 lines
1.6 KiB
C
63 lines
1.6 KiB
C
#ifndef I2C_RTL9300_H
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#define I2C_RTL9300_H
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#include <linux/i2c.h>
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#define RTL9300_I2C_CTRL1 0x00
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#define RTL9300_I2C_CTRL1_MEM_ADDR 8
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#define RTL9300_I2C_CTRL1_SDA_OUT_SEL 4
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#define RTL9300_I2C_CTRL1_GPIO8_SCL_SEL 3
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#define RTL9300_I2C_CTRL1_RWOP 2
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#define RTL9300_I2C_CTRL1_I2C_FAIL 1
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#define RTL9300_I2C_CTRL1_I2C_TRIG 0
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#define RTL9300_I2C_CTRL2 0x04
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#define RTL9300_I2C_CTRL2_DRIVE_ACK_DELAY 20
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#define RTL9300_I2C_CTRL2_CHECK_ACK_DELAY 16
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#define RTL9300_I2C_CTRL2_READ_MODE 15
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#define RTL9300_I2C_CTRL2_DEV_ADDR 8
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#define RTL9300_I2C_CTRL2_DATA_WIDTH 4
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#define RTL9300_I2C_CTRL2_MADDR_WIDTH 2
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#define RTL9300_I2C_CTRL2_SCL_FREQ 0
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#define RTL9300_I2C_DATA_WORD0 0x08
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#define RTL9300_I2C_MST_GLB_CTRL 0x18
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#define RTL9310_I2C_MST_IF_CTRL 0x00
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#define RTL9310_I2C_MST_IF_SEL 0x04
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#define RTL9310_I2C_MST_IF_SEL_GPIO_SCL_SEL 12
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#define RTL9310_I2C_CTRL 0x08
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#define RTL9310_I2C_CTRL_SCL_FREQ 30
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#define RTL9310_I2C_CTRL_CHECK_ACK_DELAY 26
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#define RTL9310_I2C_CTRL_DRIVE_ACK_DELAY 22
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#define RTL9310_I2C_CTRL_SDA_OUT_SEL 18
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#define RTL9310_I2C_CTRL_DEV_ADDR 11
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#define RTL9310_I2C_CTRL_MADDR_WIDTH 9
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#define RTL9310_I2C_CTRL_DATA_WIDTH 5
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#define RTL9310_I2C_CTRL_READ_MODE 4
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#define RTL9310_I2C_CTRL_RWOP 2
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#define RTL9310_I2C_CTRL_I2C_FAIL 1
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#define RTL9310_I2C_CTRL_I2C_TRIG 0
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#define RTL9310_I2C_MEMADDR 0x0c
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#define RTL9310_I2C_DATA 0x10
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#define RTL9300_I2C_STD_FREQ 0
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#define RTL9300_I2C_FAST_FREQ 1
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struct rtl9300_i2c {
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void __iomem *base;
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u32 mst2_offset;
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struct device *dev;
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struct i2c_adapter adap;
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u8 bus_freq;
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u8 sda_num; // SDA channel number
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u8 scl_num; // SCL channel, mapping to master 1 or 2
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};
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#endif
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