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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
30 lines
1.1 KiB
Diff
30 lines
1.1 KiB
Diff
From 52a48e8ed546339122983329410be801a2b9adf5 Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:48:35 +0100
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Subject: [PATCH] arm64: dts: qcom: ipq8074: correct Gen2 PCIe ranges
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Current ranges property set in Gen2 PCIe node is incorrect, replace it
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with the downstream 5.4 QCA kernel value.
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Fixes: 33057e1672fe ("ARM: dts: ipq8074: Add pcie nodes")
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 6 +++---
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1 file changed, 3 insertions(+), 3 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -808,9 +808,9 @@
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phy-names = "pciephy";
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ranges = <0x81000000 0 0x10200000 0x10200000
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- 0 0x100000 /* downstream I/O */
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- 0x82000000 0 0x10300000 0x10300000
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- 0 0xd00000>; /* non-prefetchable memory */
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+ 0 0x10000>, /* downstream I/O */
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+ <0x82000000 0 0x10220000 0x10220000
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+ 0 0xfde0000>; /* non-prefetchable memory */
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interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
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interrupt-names = "msi";
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