mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-26 00:41:17 +00:00
b5f32064ed
Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
131 lines
3.0 KiB
Diff
131 lines
3.0 KiB
Diff
From c3cc0c2a17f552be2426200e47a9e2c62cf449ce Mon Sep 17 00:00:00 2001
|
|
From: Robert Marko <robimarko@gmail.com>
|
|
Date: Fri, 19 Aug 2022 00:02:45 +0200
|
|
Subject: [PATCH] arm64: dts: qcom: ipq8074: add thermal nodes
|
|
|
|
IPQ8074 has a tsens v2.3.0 peripheral which monitors
|
|
temperatures around the various subsystems on the
|
|
die.
|
|
|
|
So lets add the tsens and thermal zone nodes, passive
|
|
CPU cooling will come in later patches after CPU frequency
|
|
scaling is supported.
|
|
|
|
Signed-off-by: Robert Marko <robimarko@gmail.com>
|
|
Signed-off-by: Bjorn Andersson <andersson@kernel.org>
|
|
Link: https://lore.kernel.org/r/20220818220245.338396-5-robimarko@gmail.com
|
|
---
|
|
arch/arm64/boot/dts/qcom/ipq8074.dtsi | 96 +++++++++++++++++++++++++++
|
|
1 file changed, 96 insertions(+)
|
|
|
|
--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
|
|
@@ -273,6 +273,16 @@
|
|
status = "disabled";
|
|
};
|
|
|
|
+ tsens: thermal-sensor@4a9000 {
|
|
+ compatible = "qcom,ipq8074-tsens";
|
|
+ reg = <0x4a9000 0x1000>, /* TM */
|
|
+ <0x4a8000 0x1000>; /* SROT */
|
|
+ interrupts = <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>;
|
|
+ interrupt-names = "combined";
|
|
+ #qcom,sensors = <16>;
|
|
+ #thermal-sensor-cells = <1>;
|
|
+ };
|
|
+
|
|
cryptobam: dma-controller@704000 {
|
|
compatible = "qcom,bam-v1.7.0";
|
|
reg = <0x00704000 0x20000>;
|
|
@@ -873,4 +883,90 @@
|
|
<GIC_PPI 4 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,
|
|
<GIC_PPI 1 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>;
|
|
};
|
|
+
|
|
+ thermal-zones {
|
|
+ nss-top-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 4>;
|
|
+ };
|
|
+
|
|
+ nss0-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 5>;
|
|
+ };
|
|
+
|
|
+ nss1-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 6>;
|
|
+ };
|
|
+
|
|
+ wcss-phya0-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 7>;
|
|
+ };
|
|
+
|
|
+ wcss-phya1-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 8>;
|
|
+ };
|
|
+
|
|
+ cpu0_thermal: cpu0-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 9>;
|
|
+ };
|
|
+
|
|
+ cpu1_thermal: cpu1-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 10>;
|
|
+ };
|
|
+
|
|
+ cpu2_thermal: cpu2-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 11>;
|
|
+ };
|
|
+
|
|
+ cpu3_thermal: cpu3-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 12>;
|
|
+ };
|
|
+
|
|
+ cluster_thermal: cluster-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 13>;
|
|
+ };
|
|
+
|
|
+ wcss-phyb0-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 14>;
|
|
+ };
|
|
+
|
|
+ wcss-phyb1-thermal {
|
|
+ polling-delay-passive = <250>;
|
|
+ polling-delay = <1000>;
|
|
+
|
|
+ thermal-sensors = <&tsens 15>;
|
|
+ };
|
|
+ };
|
|
};
|