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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
40 lines
1.2 KiB
Diff
40 lines
1.2 KiB
Diff
From 159cbe595c1018a0172c637374ec69af643fa9f5 Mon Sep 17 00:00:00 2001
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From: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Date: Wed, 4 May 2022 15:19:22 +0200
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Subject: [PATCH] arm64: dts: qcom: align DWC3 USB clocks with DT schema
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Align order of clocks and their names with Qualcomm DWC3 USB DT schema.
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No functional impact expected.
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Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
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Link: https://lore.kernel.org/r/20220504131923.214367-13-krzysztof.kozlowski@linaro.org
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Signed-off-by: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 8 ++++----
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1 file changed, 4 insertions(+), 4 deletions(-)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -563,8 +563,8 @@
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<&gcc GCC_USB0_MASTER_CLK>,
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<&gcc GCC_USB0_SLEEP_CLK>,
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<&gcc GCC_USB0_MOCK_UTMI_CLK>;
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- clock-names = "sys_noc_axi",
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- "master",
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+ clock-names = "cfg_noc",
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+ "core",
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"sleep",
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"mock_utmi";
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@@ -603,8 +603,8 @@
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<&gcc GCC_USB1_MASTER_CLK>,
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<&gcc GCC_USB1_SLEEP_CLK>,
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<&gcc GCC_USB1_MOCK_UTMI_CLK>;
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- clock-names = "sys_noc_axi",
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- "master",
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+ clock-names = "cfg_noc",
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+ "core",
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"sleep",
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"mock_utmi";
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