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Qualcomm Atheros IPQ807x is a modern WiSoC featuring: * Quad Core ARMv8 Cortex A-53 * @ 2.2 GHz (IPQ8072A/4A/6A/8A) Codename Hawkeye * @ 1.4 GHz (IPQ8070A/1A) Codename Acorn * Dual Band simultaneaous IEEE 802.11ax * 5G: 8x8/80 or 4x4/160MHz (IPQ8074A/8A) * 5G: 4x4/80 or 2x2/160MHz (IPQ8071A/2A/6A) * 5G: 2x2/80MHz (IPQ8070A) * 2G: 4x4/40MHz (IPQ8072A/4A/6A/8A) * 2G: 2x2/40MHz (IPQ8070A/1A) * 1x PSGMII via QCA8072/5 (Max 5x 1GbE ports) * 2x SGMII/USXGMII (1/2.5/5/10 GbE) on Hawkeye * 2x SGMII/USXGMII (1/2.5/5 GbE) on Acorn * DDR3L/4 32/16 bit up to 2400MT/s * SDIO 3.0/SD card 3.0/eMMC 5.1 * Dual USB 3.0 * One PCIe Gen2.1 and one PCIe Gen3.0 port (Single lane) * Parallel NAND (ONFI)/LCD * 6x QUP BLSP SPI/I2C/UART * I2S, PCM, and TDMA * HW PWM * 1.8V configurable GPIO * Companion PMP8074 PMIC via SPMI (GPIOS, RTC etc) Note that only v2 SOC models aka the ones ending with A suffix are supported, v1 models do not comply to the final 802.11ax and have lower clocks, lack the Gen3 PCIe etc. SoC itself has two UBI32 cores for the NSS offloading system, however currently no offloading is supported. Signed-off-by: Robert Marko <robimarko@gmail.com>
44 lines
1.4 KiB
Diff
44 lines
1.4 KiB
Diff
From adf62d2727d4aa2b587e2db59eafb5be776a653c Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Sun, 5 Sep 2021 18:58:16 +0200
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Subject: [PATCH] arm64: dts: qcom: ipq8074: add SPMI bus
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IPQ8074 uses SPMI for communication with the PMIC, so
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since its already supported add the DT node for it.
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <bjorn.andersson@linaro.org>
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Link: https://lore.kernel.org/r/20210905165816.655275-1-robimarko@gmail.com
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---
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arch/arm64/boot/dts/qcom/ipq8074.dtsi | 19 +++++++++++++++++++
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1 file changed, 19 insertions(+)
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--- a/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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+++ b/arch/arm64/boot/dts/qcom/ipq8074.dtsi
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@@ -293,6 +293,25 @@
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#reset-cells = <0x1>;
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};
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+ spmi_bus: spmi@200f000 {
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+ compatible = "qcom,spmi-pmic-arb";
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+ reg = <0x0200f000 0x001000>,
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+ <0x02400000 0x800000>,
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+ <0x02c00000 0x800000>,
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+ <0x03800000 0x200000>,
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+ <0x0200a000 0x000700>;
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+ reg-names = "core", "chnls", "obsrvr", "intr", "cnfg";
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+ interrupts = <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>;
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+ interrupt-names = "periph_irq";
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+ qcom,ee = <0>;
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+ qcom,channel = <0>;
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+ #address-cells = <2>;
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+ #size-cells = <0>;
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+ interrupt-controller;
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+ #interrupt-cells = <4>;
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+ cell-index = <0>;
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+ };
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+
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sdhc_1: sdhci@7824900 {
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compatible = "qcom,sdhci-msm-v4";
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reg = <0x7824900 0x500>, <0x7824000 0x800>;
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