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e29500eb84
Refreshed all patches. Altered patches: - 080-sata_support.patch Remove upstreamed: - 034-v4.20-MIPS-BCM47XX-Enable-USB-power-on-Netgear-WNDR3400v3.patch - 001-4.21-01-BCM63XX-fix-switch-core-reset-on-BCM6368.patch - 073-qcom-ipq4019-fix-cpu0-s-qcom-saw2-reg-value.patch Compile-tested on: cns3xxx Runtime-tested on: cns3xxx Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
54 lines
1.9 KiB
Diff
54 lines
1.9 KiB
Diff
From d8237d704fc25eb2fc25ef4403608b78c6a6d4be Mon Sep 17 00:00:00 2001
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From: Jonas Gorski <jonas.gorski@gmail.com>
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Date: Sun, 15 Jul 2012 20:08:57 +0200
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Subject: [PATCH 54/81] bcm63xx_enet: enable rgmii clock on external ports
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---
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arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h | 13 +++++++++++++
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drivers/net/ethernet/broadcom/bcm63xx_enet.c | 12 ++++++++++++
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2 files changed, 25 insertions(+), 0 deletions(-)
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--- a/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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+++ b/arch/mips/include/asm/mach-bcm63xx/bcm63xx_regs.h
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@@ -968,6 +968,19 @@
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#define ENETSW_PORTOV_FDX_MASK (1 << 1)
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#define ENETSW_PORTOV_LINKUP_MASK (1 << 0)
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+/* Port RGMII control register */
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+#define ENETSW_RGMII_CTRL_REG(x) (0x60 + (x))
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+#define ENETSW_RGMII_CTRL_GMII_CLK_EN (1 << 7)
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+#define ENETSW_RGMII_CTRL_MII_OVERRIDE_EN (1 << 6)
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+#define ENETSW_RGMII_CTRL_MII_MODE_MASK (3 << 4)
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+#define ENETSW_RGMII_CTRL_RGMII_MODE (0 << 4)
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+#define ENETSW_RGMII_CTRL_MII_MODE (1 << 4)
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+#define ENETSW_RGMII_CTRL_RVMII_MODE (2 << 4)
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+#define ENETSW_RGMII_CTRL_TIMING_SEL_EN (1 << 0)
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+
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+/* Port RGMII timing register */
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+#define ENETSW_RGMII_TIMING_REG(x) (0x68 + (x))
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+
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/* MDIO control register */
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#define ENETSW_MDIOC_REG (0xb0)
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#define ENETSW_MDIOC_EXT_MASK (1 << 16)
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--- a/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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+++ b/drivers/net/ethernet/broadcom/bcm63xx_enet.c
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@@ -2185,6 +2185,18 @@ static int bcm_enetsw_open(struct net_de
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priv->sw_port_link[i] = 0;
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}
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+ /* enable external ports */
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+ for (i = ENETSW_RGMII_PORT0; i < priv->num_ports; i++) {
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+ u8 rgmii_ctrl;
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+
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+ if (!priv->used_ports[i].used)
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+ continue;
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+
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+ rgmii_ctrl = enetsw_readb(priv, ENETSW_RGMII_CTRL_REG(i));
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+ rgmii_ctrl |= ENETSW_RGMII_CTRL_GMII_CLK_EN;
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+ enetsw_writeb(priv, rgmii_ctrl, ENETSW_RGMII_CTRL_REG(i));
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+ }
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+
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/* reset mib */
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val = enetsw_readb(priv, ENETSW_GMCR_REG);
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val |= ENETSW_GMCR_RST_MIB_MASK;
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