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https://github.com/openwrt/openwrt.git
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84d489f64f
Changelog: https://cdn.kernel.org/pub/linux/kernel/v4.x/ChangeLog-4.4.14 Some manual changes to target/linux/generic/patches-4.4/610- netfilter_match_bypass_default_checks.patch were needed. Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
130 lines
3.5 KiB
Diff
130 lines
3.5 KiB
Diff
From 16d2871830ff3fe12a6bff582549a9264adff278 Mon Sep 17 00:00:00 2001
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From: Ram Chandra Jangir <rjangi@codeaurora.org>
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Date: Tue, 10 May 2016 20:19:31 +0530
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Subject: [PATCH] spi: qup: Fix fifo and dma support for IPQ806x
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Signed-off-by: Ram Chandra Jangir <rjangi@codeaurora.org>
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---
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drivers/spi/spi-qup.c | 54 +++++++++++++++++++++++++++++++++++++++++++++++++--
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1 file changed, 52 insertions(+), 2 deletions(-)
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--- a/drivers/spi/spi-qup.c
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+++ b/drivers/spi/spi-qup.c
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@@ -24,6 +24,7 @@
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#include <linux/spi/spi.h>
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#include <linux/dmaengine.h>
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#include <linux/dma-mapping.h>
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+#include <linux/gpio.h>
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#define QUP_CONFIG 0x0000
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#define QUP_STATE 0x0004
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@@ -152,6 +153,7 @@ struct spi_qup {
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int use_dma;
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struct dma_slave_config rx_conf;
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struct dma_slave_config tx_conf;
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+ int mode;
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};
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@@ -370,7 +372,8 @@ static int spi_qup_do_pio(struct spi_mas
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return ret;
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}
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- spi_qup_fifo_write(qup, xfer);
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+ if (qup->mode == QUP_IO_M_MODE_FIFO)
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+ spi_qup_fifo_write(qup, xfer);
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return 0;
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}
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@@ -448,6 +451,7 @@ spi_qup_get_mode(struct spi_master *mast
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{
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struct spi_qup *qup = spi_master_get_devdata(master);
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u32 mode;
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+ size_t dma_align = dma_get_cache_alignment();
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qup->w_size = 4;
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@@ -458,6 +462,14 @@ spi_qup_get_mode(struct spi_master *mast
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qup->n_words = xfer->len / qup->w_size;
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+ if (!IS_ERR_OR_NULL(master->dma_rx) &&
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+ IS_ALIGNED((size_t)xfer->tx_buf, dma_align) &&
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+ IS_ALIGNED((size_t)xfer->rx_buf, dma_align) &&
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+ !is_vmalloc_addr(xfer->tx_buf) &&
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+ !is_vmalloc_addr(xfer->rx_buf) &&
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+ (xfer->len > 3*qup->in_blk_sz))
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+ qup->use_dma = 1;
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+
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if (qup->n_words <= (qup->in_fifo_sz / sizeof(u32)))
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mode = QUP_IO_M_MODE_FIFO;
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else
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@@ -491,7 +503,7 @@ static int spi_qup_io_config(struct spi_
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return -EIO;
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}
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- mode = spi_qup_get_mode(spi->master, xfer);
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+ controller->mode = mode = spi_qup_get_mode(spi->master, xfer);
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n_words = controller->n_words;
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if (mode == QUP_IO_M_MODE_FIFO) {
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@@ -500,6 +512,7 @@ static int spi_qup_io_config(struct spi_
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/* must be zero for FIFO */
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writel_relaxed(0, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(0, controller->base + QUP_MX_OUTPUT_CNT);
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+ controller->use_dma = 0;
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} else if (!controller->use_dma) {
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writel_relaxed(n_words, controller->base + QUP_MX_INPUT_CNT);
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writel_relaxed(n_words, controller->base + QUP_MX_OUTPUT_CNT);
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@@ -750,6 +763,38 @@ err_tx:
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return ret;
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}
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+static void spi_qup_set_cs(struct spi_device *spi, bool val)
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+{
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+ struct spi_qup *controller;
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+ u32 spi_ioc;
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+ u32 spi_ioc_orig;
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+
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+ controller = spi_master_get_devdata(spi->master);
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+ spi_ioc = readl_relaxed(controller->base + SPI_IO_CONTROL);
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+ spi_ioc_orig = spi_ioc;
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+ if (!val)
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+ spi_ioc |= SPI_IO_C_FORCE_CS;
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+ else
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+ spi_ioc &= ~SPI_IO_C_FORCE_CS;
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+
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+ if (spi_ioc != spi_ioc_orig)
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+ writel_relaxed(spi_ioc, controller->base + SPI_IO_CONTROL);
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+}
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+
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+static int spi_qup_setup(struct spi_device *spi)
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+{
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+ if (spi->cs_gpio >= 0) {
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+ if (spi->mode & SPI_CS_HIGH)
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+ gpio_set_value(spi->cs_gpio, 0);
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+ else
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+ gpio_set_value(spi->cs_gpio, 1);
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+
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+ udelay(10);
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+ }
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+
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+ return 0;
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+}
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+
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static int spi_qup_probe(struct platform_device *pdev)
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{
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struct spi_master *master;
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@@ -846,6 +891,11 @@ static int spi_qup_probe(struct platform
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if (of_device_is_compatible(dev->of_node, "qcom,spi-qup-v1.1.1"))
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controller->qup_v1 = 1;
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+ if (!controller->qup_v1)
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+ master->set_cs = spi_qup_set_cs;
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+ else
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+ master->setup = spi_qup_setup;
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+
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spin_lock_init(&controller->lock);
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init_completion(&controller->done);
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