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2e715fb4fc
Add support for BCM2712 (Raspberry Pi 5).
3bb5880ab3
Patches were generated from the diff between linux kernel branch linux-6.1.y
and rpi-6.1.y from raspberry pi kernel source:
- git format-patch linux-6.1.y...rpi-6.1.y
Build system: x86_64
Build-tested: bcm2708, bcm2709, bcm2710, bcm2711
Run-tested: bcm2710/RPi3B, bcm2711/RPi4B
Signed-off-by: Marty Jones <mj8263788@gmail.com>
[Remove applied and reverted patches, squash patches and config commits]
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
293 lines
7.3 KiB
Diff
293 lines
7.3 KiB
Diff
From 824f18efc8ad59e2783570ae2df83e2cd16b9f04 Mon Sep 17 00:00:00 2001
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From: Phil Elwell <phil@raspberrypi.com>
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Date: Tue, 14 Feb 2023 14:03:54 +0000
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Subject: [PATCH] pwm: Add support for RP1 PWM
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Add a driver for the RP1 PWM block.
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Signed-off-by: Phil Elwell <phil@raspberrypi.com>
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---
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.../devicetree/bindings/pwm/pwm-rp1.yaml | 38 ++++
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drivers/pwm/Kconfig | 9 +
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drivers/pwm/Makefile | 1 +
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drivers/pwm/pwm-rp1.c | 203 ++++++++++++++++++
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4 files changed, 251 insertions(+)
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create mode 100644 Documentation/devicetree/bindings/pwm/pwm-rp1.yaml
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create mode 100644 drivers/pwm/pwm-rp1.c
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--- /dev/null
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+++ b/Documentation/devicetree/bindings/pwm/pwm-rp1.yaml
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@@ -0,0 +1,38 @@
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+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
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+%YAML 1.2
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+---
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+$id: http://devicetree.org/schemas/pwm/pwm-rp1.yaml#
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+$schema: http://devicetree.org/meta-schemas/core.yaml#
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+
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+title: Raspberry Pi RP1 PWM controller
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+
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+maintainers:
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+ - Naushir Patuck <naush@raspberrypi.com>
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+
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+properties:
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+ compatible:
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+ enum:
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+ - raspberrypi,rp1-pwm
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+
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+ reg:
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+ maxItems: 1
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+
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+ "#pwm-cells":
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+ const: 3
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+
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+required:
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+ - compatible
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+ - reg
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+ - clocks
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+ - "#pwm-cells"
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+
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+additionalProperties: false
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+
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+examples:
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+ - |
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+ pwm0: pwm@98000 {
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+ compatible = "raspberrypi,rp1-pwm";
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+ reg = <0x0 0x98000 0x0 0x100>;
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+ clocks = <&rp1_sys>;
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+ #pwm-cells = <3>;
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+ };
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--- a/drivers/pwm/Kconfig
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+++ b/drivers/pwm/Kconfig
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@@ -451,6 +451,15 @@ config PWM_RASPBERRYPI_POE
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Enable Raspberry Pi firmware controller PWM bus used to control the
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official RPI PoE hat
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+config PWM_RP1
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+ tristate "RP1 PWM support"
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+ depends on ARCH_BCM2835 || COMPILE_TEST
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+ help
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+ PWM framework driver for Raspberry Pi RP1 controller
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+
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+ To compile this driver as a module, choose M here: the module
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+ will be called pwm-rp1.
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+
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config PWM_RCAR
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tristate "Renesas R-Car PWM support"
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depends on ARCH_RENESAS || COMPILE_TEST
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--- a/drivers/pwm/Makefile
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+++ b/drivers/pwm/Makefile
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@@ -41,6 +41,7 @@ obj-$(CONFIG_PWM_OMAP_DMTIMER) += pwm-om
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obj-$(CONFIG_PWM_PCA9685) += pwm-pca9685.o
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obj-$(CONFIG_PWM_PXA) += pwm-pxa.o
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obj-$(CONFIG_PWM_RASPBERRYPI_POE) += pwm-raspberrypi-poe.o
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+obj-$(CONFIG_PWM_RP1) += pwm-rp1.o
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obj-$(CONFIG_PWM_RCAR) += pwm-rcar.o
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obj-$(CONFIG_PWM_RENESAS_TPU) += pwm-renesas-tpu.o
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obj-$(CONFIG_PWM_ROCKCHIP) += pwm-rockchip.o
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--- /dev/null
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+++ b/drivers/pwm/pwm-rp1.c
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@@ -0,0 +1,203 @@
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+// SPDX-License-Identifier: GPL-2.0
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+/*
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+ * pwm-rp1.c
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+ *
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+ * Raspberry Pi RP1 PWM.
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+ *
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+ * Copyright © 2023 Raspberry Pi Ltd.
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+ *
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+ * Author: Naushir Patuck (naush@raspberrypi.com)
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+ *
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+ * Based on the pwm-bcm2835 driver by:
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+ * Bart Tanghe <bart.tanghe@thomasmore.be>
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+ */
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+
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+#include <linux/bitops.h>
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+#include <linux/clk.h>
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+#include <linux/err.h>
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+#include <linux/io.h>
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+#include <linux/module.h>
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+#include <linux/of.h>
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+#include <linux/platform_device.h>
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+#include <linux/pwm.h>
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+
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+#define PWM_GLOBAL_CTRL 0x000
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+#define PWM_CHANNEL_CTRL(x) (0x014 + ((x) * 16))
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+#define PWM_RANGE(x) (0x018 + ((x) * 16))
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+#define PWM_DUTY(x) (0x020 + ((x) * 16))
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+
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+/* 8:FIFO_POP_MASK + 0:Trailing edge M/S modulation */
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+#define PWM_CHANNEL_DEFAULT (BIT(8) + BIT(0))
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+#define PWM_CHANNEL_ENABLE(x) BIT(x)
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+#define PWM_POLARITY BIT(3)
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+#define SET_UPDATE BIT(31)
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+#define PWM_MODE_MASK GENMASK(1, 0)
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+
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+struct rp1_pwm {
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+ struct pwm_chip chip;
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+ struct device *dev;
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+ void __iomem *base;
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+ struct clk *clk;
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+};
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+
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+static inline struct rp1_pwm *to_rp1_pwm(struct pwm_chip *chip)
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+{
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+ return container_of(chip, struct rp1_pwm, chip);
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+}
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+
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+static void rp1_pwm_apply_config(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct rp1_pwm *pc = to_rp1_pwm(chip);
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+ u32 value;
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+
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+ value = readl(pc->base + PWM_GLOBAL_CTRL);
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+ value |= SET_UPDATE;
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+ writel(value, pc->base + PWM_GLOBAL_CTRL);
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+}
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+
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+static int rp1_pwm_request(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct rp1_pwm *pc = to_rp1_pwm(chip);
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+
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+ writel(PWM_CHANNEL_DEFAULT, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
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+ return 0;
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+}
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+
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+static void rp1_pwm_free(struct pwm_chip *chip, struct pwm_device *pwm)
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+{
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+ struct rp1_pwm *pc = to_rp1_pwm(chip);
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+ u32 value;
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+
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+ value = readl(pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
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+ value &= ~PWM_MODE_MASK;
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+ writel(value, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
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+ rp1_pwm_apply_config(chip, pwm);
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+}
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+
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+static int rp1_pwm_apply(struct pwm_chip *chip, struct pwm_device *pwm,
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+ const struct pwm_state *state)
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+{
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+ struct rp1_pwm *pc = to_rp1_pwm(chip);
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+ unsigned long clk_rate = clk_get_rate(pc->clk);
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+ unsigned long clk_period;
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+ u32 value;
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+
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+ if (!clk_rate) {
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+ dev_err(pc->dev, "failed to get clock rate\n");
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+ return -EINVAL;
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+ }
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+
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+ /* set period */
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+ clk_period = DIV_ROUND_CLOSEST(NSEC_PER_SEC, clk_rate);
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+
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+ writel(DIV_ROUND_CLOSEST(state->duty_cycle, clk_period),
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+ pc->base + PWM_DUTY(pwm->hwpwm));
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+
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+ /* set duty cycle */
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+ writel(DIV_ROUND_CLOSEST(state->period, clk_period),
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+ pc->base + PWM_RANGE(pwm->hwpwm));
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+
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+ /* set polarity */
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+ value = readl(pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
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+ if (state->polarity == PWM_POLARITY_NORMAL)
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+ value &= ~PWM_POLARITY;
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+ else
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+ value |= PWM_POLARITY;
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+ writel(value, pc->base + PWM_CHANNEL_CTRL(pwm->hwpwm));
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+
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+ /* enable/disable */
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+ value = readl(pc->base + PWM_GLOBAL_CTRL);
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+ if (state->enabled)
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+ value |= PWM_CHANNEL_ENABLE(pwm->hwpwm);
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+ else
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+ value &= ~PWM_CHANNEL_ENABLE(pwm->hwpwm);
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+ writel(value, pc->base + PWM_GLOBAL_CTRL);
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+
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+ rp1_pwm_apply_config(chip, pwm);
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+
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+ return 0;
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+}
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+
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+static const struct pwm_ops rp1_pwm_ops = {
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+ .request = rp1_pwm_request,
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+ .free = rp1_pwm_free,
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+ .apply = rp1_pwm_apply,
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+ .owner = THIS_MODULE,
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+};
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+
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+static int rp1_pwm_probe(struct platform_device *pdev)
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+{
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+ struct rp1_pwm *pc;
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+ struct resource *res;
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+ int ret;
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+
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+ pc = devm_kzalloc(&pdev->dev, sizeof(*pc), GFP_KERNEL);
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+ if (!pc)
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+ return -ENOMEM;
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+
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+ pc->dev = &pdev->dev;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ pc->base = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(pc->base))
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+ return PTR_ERR(pc->base);
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+
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+ pc->clk = devm_clk_get(&pdev->dev, NULL);
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+ if (IS_ERR(pc->clk))
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+ return dev_err_probe(&pdev->dev, PTR_ERR(pc->clk),
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+ "clock not found\n");
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+
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+ ret = clk_prepare_enable(pc->clk);
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+ if (ret)
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+ return ret;
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+
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+ pc->chip.dev = &pdev->dev;
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+ pc->chip.ops = &rp1_pwm_ops;
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+ pc->chip.base = -1;
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+ pc->chip.npwm = 4;
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+ pc->chip.of_xlate = of_pwm_xlate_with_flags;
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+ pc->chip.of_pwm_n_cells = 3;
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+
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+ platform_set_drvdata(pdev, pc);
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+
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+ ret = pwmchip_add(&pc->chip);
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+ if (ret < 0)
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+ goto add_fail;
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+
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+ return 0;
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+
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+add_fail:
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+ clk_disable_unprepare(pc->clk);
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+ return ret;
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+}
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+
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+static int rp1_pwm_remove(struct platform_device *pdev)
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+{
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+ struct rp1_pwm *pc = platform_get_drvdata(pdev);
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+
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+ clk_disable_unprepare(pc->clk);
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+
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+ pwmchip_remove(&pc->chip);
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+
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+ return 0;
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+}
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+
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+static const struct of_device_id rp1_pwm_of_match[] = {
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+ { .compatible = "raspberrypi,rp1-pwm" },
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+ { /* sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(of, rp1_pwm_of_match);
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+
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+static struct platform_driver rp1_pwm_driver = {
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+ .driver = {
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+ .name = "rpi-pwm",
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+ .of_match_table = rp1_pwm_of_match,
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+ },
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+ .probe = rp1_pwm_probe,
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+ .remove = rp1_pwm_remove,
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+};
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+module_platform_driver(rp1_pwm_driver);
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+
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+MODULE_AUTHOR("Naushir Patuck <naush@raspberrypi.com");
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+MODULE_DESCRIPTION("RP1 PWM driver");
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+MODULE_LICENSE("GPL");
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