mirror of
https://github.com/openwrt/openwrt.git
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67d998e25d
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.145
No patches needed a rebase.
23.05 backport:
Rebased patch mediatek/100-dts-update-mt7622-rfb1.patch due to
changes introduced in commit e37aa926447f ("arm64: dts: mediatek:
mt7622: fix memory node warning check") in version v5.15.143 and we
jumped over from v5.15.139 directly to v5.15.145.
Build system: x86_64
Build-tested: ramips/tplink_archer-a6-v3
Run-tested: ramips/tplink_archer-a6-v3
23.05 backport:
Stijn:
Compile-tested: ath79/generic, ipq40xx/generic, mvebu/cortexa72, ramips/mt{7621,7620,76x8}, realtek/rtl{838x,930x}, 86/64.
Run-tested: cortexa72 (RB5009UG+S+IN), mt7621 (EAP615-Wall v1), rtl838x (GS1900-10HP, GS1900-8HP, GS108T v3).
Petr:
Compile-tested: ipq807x, mvebu/cortexa9
Run-tested: turris-omnia, prpl-haze
Tested-by: Stijn Segers <foss@volatilesystems.org> [23.05 testing]
Signed-off-by: John Audia <therealgraysky@proton.me>
Signed-off-by: Petr Štetiar <ynezz@true.cz> [23.05 refresh]
(cherry picked from commit 8de4cc77a6)
153 lines
6.1 KiB
Diff
153 lines
6.1 KiB
Diff
From 78936d46470938caa9a7ea529deeb36777b4f98e Mon Sep 17 00:00:00 2001
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From: Robert Marko <robimarko@gmail.com>
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Date: Wed, 16 Nov 2022 22:46:55 +0100
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Subject: [PATCH] clk: qcom: ipq8074: populate fw_name for all parents
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It appears that having only .name populated in parent_data for clocks
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which are only globally searchable currently will not work as the clk core
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won't copy that name if there is no .fw_name present as well.
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So, populate .fw_name for all parent clocks in parent_data.
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Fixes: ae55ad32e273 ("clk: qcom: ipq8074: convert to parent data")
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Co-developed-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Signed-off-by: Robert Marko <robimarko@gmail.com>
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Signed-off-by: Bjorn Andersson <andersson@kernel.org>
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Link: https://lore.kernel.org/r/20221116214655.1116467-1-robimarko@gmail.com
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---
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drivers/clk/qcom/gcc-ipq8074.c | 52 +++++++++++++++++-----------------
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1 file changed, 26 insertions(+), 26 deletions(-)
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--- a/drivers/clk/qcom/gcc-ipq8074.c
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+++ b/drivers/clk/qcom/gcc-ipq8074.c
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@@ -674,7 +674,7 @@ static struct clk_rcg2 pcie0_aux_clk_src
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};
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static const struct clk_parent_data gcc_pcie20_phy0_pipe_clk_xo[] = {
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- { .name = "pcie20_phy0_pipe_clk" },
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+ { .fw_name = "pcie0_pipe", .name = "pcie20_phy0_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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@@ -727,7 +727,7 @@ static struct clk_rcg2 pcie1_aux_clk_src
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};
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static const struct clk_parent_data gcc_pcie20_phy1_pipe_clk_xo[] = {
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- { .name = "pcie20_phy1_pipe_clk" },
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+ { .fw_name = "pcie1_pipe", .name = "pcie20_phy1_pipe_clk" },
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{ .fw_name = "xo", .name = "xo" },
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};
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@@ -1131,7 +1131,7 @@ static const struct freq_tbl ftbl_nss_no
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static const struct clk_parent_data gcc_xo_bias_pll_nss_noc_clk_gpll0_gpll2[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "bias_pll_nss_noc_clk" },
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+ { .fw_name = "bias_pll_nss_noc_clk", .name = "bias_pll_nss_noc_clk" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll2.clkr.hw },
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};
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@@ -1356,7 +1356,7 @@ static const struct freq_tbl ftbl_nss_pp
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static const struct clk_parent_data gcc_xo_bias_gpll0_gpll4_nss_ubi32[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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{ .hw = &gpll0.clkr.hw },
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{ .hw = &gpll4.clkr.hw },
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{ .hw = &nss_crypto_pll.clkr.hw },
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@@ -1407,10 +1407,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_rx_tx_ubi32_bias_map[] = {
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@@ -1459,10 +1459,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy0_tx_rx_ubi32_bias_map[] = {
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@@ -1690,12 +1690,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_rx_tx_uniphy1_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy1_gcc_rx_clk" },
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- { .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -1752,12 +1752,12 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy0_tx_rx_uniphy1_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy0_gcc_tx_clk" },
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- { .name = "uniphy0_gcc_rx_clk" },
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- { .name = "uniphy1_gcc_tx_clk" },
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- { .name = "uniphy1_gcc_rx_clk" },
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+ { .fw_name = "uniphy0_gcc_tx_clk", .name = "uniphy0_gcc_tx_clk" },
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+ { .fw_name = "uniphy0_gcc_rx_clk", .name = "uniphy0_gcc_rx_clk" },
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+ { .fw_name = "uniphy1_gcc_tx_clk", .name = "uniphy1_gcc_tx_clk" },
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+ { .fw_name = "uniphy1_gcc_rx_clk", .name = "uniphy1_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map
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@@ -1814,10 +1814,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy2_rx_tx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy2_gcc_rx_clk" },
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- { .name = "uniphy2_gcc_tx_clk" },
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+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
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+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy2_rx_tx_ubi32_bias_map[] = {
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@@ -1871,10 +1871,10 @@ static const struct freq_tbl ftbl_nss_po
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static const struct clk_parent_data gcc_xo_uniphy2_tx_rx_ubi32_bias[] = {
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{ .fw_name = "xo", .name = "xo" },
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- { .name = "uniphy2_gcc_tx_clk" },
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- { .name = "uniphy2_gcc_rx_clk" },
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+ { .fw_name = "uniphy2_gcc_tx_clk", .name = "uniphy2_gcc_tx_clk" },
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+ { .fw_name = "uniphy2_gcc_rx_clk", .name = "uniphy2_gcc_rx_clk" },
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{ .hw = &ubi32_pll.clkr.hw },
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- { .name = "bias_pll_cc_clk" },
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+ { .fw_name = "bias_pll_cc_clk", .name = "bias_pll_cc_clk" },
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};
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static const struct parent_map gcc_xo_uniphy2_tx_rx_ubi32_bias_map[] = {
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