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Hardware specification ---------------------- * RTL8380M SoC, 1 MIPS 4KEc core @ 500MHz * 256MB DRAM * 32MB NOR Flash * 8 x 10/100/1000BASE-T ports * 2 x SFP ports * Power LED, Fault LED * Reset button on front panel * UART (115200 8N1) via populated standard pin header marked JP1 TODO: The SFP ports use a shared SCL GPIO that the driver cannot handle. The left SFP port (lan9) is defined and fully functional while the laser on the right SFP port (lan10) is off by default. UART pinout ----------- [o]ooo|JP1 | ||`------ GND | |`------- RX | `-------- TX `---------- Vcc (3V3) Installation using OEM webinterface ----------------------------------- 1. Make sure you are running OEM firmware in secondary slot 2. Install squashfs-factory.imag to primary slot by upload via http Installation using serial interface ----------------------------------- 1. Press "a" "c" "p" during message "Enter correct key to stop autoboot" 2. Load image with "upgrade runtime <TFTP IP>:squashfs-sysupgrade.bin" command 3. Switch to primary slot with "setsys bootpartition 0" 4. Store config with "savesys" 5. Boot the image with `boota` command Dual-boot with stock firmware using writable u-boot-env ------------------------------------------------------- From stock to OpenWrt / primary image 1 (CLI as admin): - > boot system image1 - > reboot From OpenWrt to stock / boot image 2: (shell as root) - # fw_setsys bootpartition 1 - # reboot Debrick using serial interface ------------------------------ 1. Press "a" "c" "p" during message "Enter correct key to stop autoboot" 2. Load vendor image with "upgrade runtime <TFTP IP>:LGS310xxxxx.imag" 3. switch to primary partition "setsys bootpartition 0" 4. safe config "savesys" Further documentation --------------------- See https://openwrt.org/toh/linksys/lgs352c It has been developed and tested on device with v1 revision. Signed-off-by: Markus Stockhausen <markus.stockhausen@gmx.de> Link: https://github.com/openwrt/openwrt/pull/16068 [Add missing 'w' in name of firmware partition] Signed-off-by: Sander Vanheule <sander@svanheule.net>
213 lines
4.1 KiB
Plaintext
213 lines
4.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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#include <dt-bindings/gpio/gpio.h>
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#include "rtl838x.dtsi"
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/ {
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compatible = "linksys,lgs310c", "realtek,rtl838x-soc";
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model = "Linksys LGS310C";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_fault;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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memory@0 {
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device_type = "memory";
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reg = <0x0 0x10000000>;
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};
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leds: leds {
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pinctrl-names = "default";
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pinctrl-0 = <&pinmux_disable_sys_led>;
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compatible = "gpio-leds";
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led_power: led-0 {
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function = LED_FUNCTION_POWER;
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color = <LED_COLOR_ID_GREEN>;
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gpios = <&gpio1 3 GPIO_ACTIVE_LOW>;
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};
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led_fault: led-1 {
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function = LED_FUNCTION_FAULT;
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color = <LED_COLOR_ID_AMBER>;
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gpios = <&gpio1 2 GPIO_ACTIVE_LOW>;
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};
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};
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/* i2c of the left SFP cage: port 9 */
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i2c0: i2c-gpio-0 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 6 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp0: sfp-p9 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c0>;
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los-gpio = <&gpio1 11 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 12 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 10 GPIO_ACTIVE_HIGH>;
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};
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/* i2c of the right SFP cage: port 10 */
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i2c1: i2c-gpio-1 {
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compatible = "i2c-gpio";
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sda-gpios = <&gpio1 7 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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/*
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* ports 9 & 10 use a shared SCL, and are currently not usable in parallel
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* So for now disable the SCL on the second port.
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*
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* scl-gpios = <&gpio1 31 (GPIO_ACTIVE_HIGH | GPIO_OPEN_DRAIN)>;
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*/
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i2c-gpio,scl-open-drain;
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i2c-gpio,delay-us = <2>;
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#address-cells = <1>;
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#size-cells = <0>;
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};
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sfp1: sfp-p10 {
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compatible = "sff,sfp";
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i2c-bus = <&i2c1>;
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los-gpio = <&gpio1 14 GPIO_ACTIVE_HIGH>;
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mod-def0-gpio = <&gpio1 21 GPIO_ACTIVE_LOW>;
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tx-disable-gpio = <&gpio1 13 GPIO_ACTIVE_HIGH>;
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio0 11 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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};
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gpio1: rtl8231-gpio {
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compatible = "realtek,rtl8231-gpio";
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#gpio-cells = <2>;
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gpio-controller;
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indirect-access-bus-id = <0>;
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};
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <10000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x00000000 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "u-boot-env";
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reg = <0x00080000 0x10000>;
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};
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partition@90000 {
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label = "u-boot-env2";
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reg = <0x00090000 0x10000>;
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};
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partition@a0000 {
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label = "jffs2";
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reg = <0x000a0000 0x500000>;
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};
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partition@5a0000 {
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label = "firmware";
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compatible = "openwrt,uimage";
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reg = <0x005a0000 0xd30000>;
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};
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partition@2d0000 {
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label = "kernel2";
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reg = <0x012d0000 0xd30000>;
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};
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};
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};
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};
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&uart1 {
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status = "okay";
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};
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ðernet0 {
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mdio: mdio-bus {
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compatible = "realtek,rtl838x-mdio";
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regmap = <ðernet0>;
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#address-cells = <1>;
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#size-cells = <0>;
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INTERNAL_PHY(8)
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INTERNAL_PHY(9)
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INTERNAL_PHY(10)
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INTERNAL_PHY(11)
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INTERNAL_PHY(12)
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INTERNAL_PHY(13)
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INTERNAL_PHY(14)
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INTERNAL_PHY(15)
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INTERNAL_PHY(24)
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INTERNAL_PHY(26)
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};
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};
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&switch0 {
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ports {
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#address-cells = <1>;
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#size-cells = <0>;
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SWITCH_PORT(8, 1, internal)
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SWITCH_PORT(9, 2, internal)
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SWITCH_PORT(10, 3, internal)
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SWITCH_PORT(11, 4, internal)
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SWITCH_PORT(12, 5, internal)
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SWITCH_PORT(13, 6, internal)
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SWITCH_PORT(14, 7, internal)
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SWITCH_PORT(15, 8, internal)
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port@24 {
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reg = <24>;
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label = "lan9";
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phy-handle = <&phy24>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp0>;
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};
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port@26 {
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reg = <26>;
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label = "lan10";
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phy-handle = <&phy26>;
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phy-mode = "1000base-x";
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managed = "in-band-status";
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sfp = <&sfp1>;
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};
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port@28 {
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ethernet = <ðernet0>;
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reg = <28>;
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phy-mode = "internal";
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fixed-link {
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speed = <1000>;
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full-duplex;
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};
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};
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};
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};
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