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61a2bedf79
Replace lcc patch with proposed upstream version. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
218 lines
6.2 KiB
Diff
218 lines
6.2 KiB
Diff
From 92ef900a4a53b62e0dc32554eb088a422657606c Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Wed, 15 Jun 2022 17:35:13 +0200
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Subject: [PATCH v5 3/3] clk: qcom: lcc-ipq806x: convert to parent data
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Convert lcc-ipq806x driver to parent_data API.
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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---
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v5:
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- Fix the same compilation error (don't know what the hell happen
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to my buildroot)
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v4:
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- Fix compilation error
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v3:
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- Inline pxo pll4 parent
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- Change .name from pxo to pxo_board
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drivers/clk/qcom/lcc-ipq806x.c | 77 ++++++++++++++++++----------------
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1 file changed, 42 insertions(+), 35 deletions(-)
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--- a/drivers/clk/qcom/lcc-ipq806x.c
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+++ b/drivers/clk/qcom/lcc-ipq806x.c
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@@ -34,7 +34,9 @@ static struct clk_pll pll4 = {
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.status_bit = 16,
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.clkr.hw.init = &(struct clk_init_data){
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.name = "pll4",
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- .parent_names = (const char *[]){ "pxo" },
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+ .parent_data = &(const struct clk_parent_data) {
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+ .fw_name = "pxo", .name = "pxo_board",
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+ },
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.num_parents = 1,
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.ops = &clk_pll_ops,
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},
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@@ -64,9 +66,9 @@ static const struct parent_map lcc_pxo_p
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{ P_PLL4, 2 }
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};
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-static const char * const lcc_pxo_pll4[] = {
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- "pxo",
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- "pll4_vote",
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+static const struct clk_parent_data lcc_pxo_pll4[] = {
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+ { .fw_name = "pxo", .name = "pxo" },
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+ { .fw_name = "pll4_vote", .name = "pll4_vote" },
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};
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static struct freq_tbl clk_tbl_aif_mi2s[] = {
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@@ -131,18 +133,14 @@ static struct clk_rcg mi2s_osr_src = {
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_src",
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- .parent_names = lcc_pxo_pll4,
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- .num_parents = 2,
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+ .parent_data = lcc_pxo_pll4,
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+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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-static const char * const lcc_mi2s_parents[] = {
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- "mi2s_osr_src",
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-};
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-
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static struct clk_branch mi2s_osr_clk = {
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.halt_reg = 0x50,
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.halt_bit = 1,
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@@ -152,7 +150,9 @@ static struct clk_branch mi2s_osr_clk =
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.enable_mask = BIT(17),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_osr_clk",
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- .parent_names = lcc_mi2s_parents,
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+ .parent_hws = (const struct clk_hw*[]){
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+ &mi2s_osr_src.clkr.hw,
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+ },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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@@ -167,7 +167,9 @@ static struct clk_regmap_div mi2s_div_cl
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_div_clk",
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- .parent_names = lcc_mi2s_parents,
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+ .parent_hws = (const struct clk_hw*[]){
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+ &mi2s_osr_src.clkr.hw,
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+ },
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.num_parents = 1,
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.ops = &clk_regmap_div_ops,
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},
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@@ -183,7 +185,9 @@ static struct clk_branch mi2s_bit_div_cl
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.enable_mask = BIT(15),
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_div_clk",
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- .parent_names = (const char *[]){ "mi2s_div_clk" },
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+ .parent_hws = (const struct clk_hw*[]){
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+ &mi2s_div_clk.clkr.hw,
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+ },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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@@ -191,6 +195,10 @@ static struct clk_branch mi2s_bit_div_cl
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},
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};
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+static const struct clk_parent_data lcc_mi2s_bit_div_codec_clk[] = {
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+ { .hw = &mi2s_bit_div_clk.clkr.hw, },
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+ { .fw_name = "mi2s_codec_clk", .name = "mi2s_codec_clk" },
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+};
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static struct clk_regmap_mux mi2s_bit_clk = {
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.reg = 0x48,
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@@ -199,11 +207,8 @@ static struct clk_regmap_mux mi2s_bit_cl
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "mi2s_bit_clk",
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- .parent_names = (const char *[]){
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- "mi2s_bit_div_clk",
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- "mi2s_codec_clk",
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- },
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- .num_parents = 2,
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+ .parent_data = lcc_mi2s_bit_div_codec_clk,
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+ .num_parents = ARRAY_SIZE(lcc_mi2s_bit_div_codec_clk),
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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@@ -245,8 +250,8 @@ static struct clk_rcg pcm_src = {
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_src",
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- .parent_names = lcc_pxo_pll4,
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- .num_parents = 2,
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+ .parent_data = lcc_pxo_pll4,
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+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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@@ -262,7 +267,9 @@ static struct clk_branch pcm_clk_out = {
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk_out",
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- .parent_names = (const char *[]){ "pcm_src" },
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+ .parent_hws = (const struct clk_hw*[]){
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+ &pcm_src.clkr.hw,
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+ },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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@@ -270,6 +277,11 @@ static struct clk_branch pcm_clk_out = {
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},
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};
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+static const struct clk_parent_data lcc_pcm_clk_out_codec_clk[] = {
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+ { .hw = &pcm_clk_out.clkr.hw, },
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+ { .fw_name = "pcm_codec_clk", .name = "pcm_codec_clk" },
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+};
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+
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static struct clk_regmap_mux pcm_clk = {
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.reg = 0x54,
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.shift = 10,
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@@ -277,11 +289,8 @@ static struct clk_regmap_mux pcm_clk = {
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.clkr = {
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.hw.init = &(struct clk_init_data){
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.name = "pcm_clk",
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- .parent_names = (const char *[]){
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- "pcm_clk_out",
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- "pcm_codec_clk",
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- },
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- .num_parents = 2,
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+ .parent_data = lcc_pcm_clk_out_codec_clk,
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+ .num_parents = ARRAY_SIZE(lcc_pcm_clk_out_codec_clk),
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.ops = &clk_regmap_mux_closest_ops,
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.flags = CLK_SET_RATE_PARENT,
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},
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@@ -325,18 +334,14 @@ static struct clk_rcg spdif_src = {
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.enable_mask = BIT(9),
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.hw.init = &(struct clk_init_data){
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.name = "spdif_src",
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- .parent_names = lcc_pxo_pll4,
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- .num_parents = 2,
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+ .parent_data = lcc_pxo_pll4,
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+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_ops,
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.flags = CLK_SET_RATE_GATE,
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},
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},
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};
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-static const char * const lcc_spdif_parents[] = {
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- "spdif_src",
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-};
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-
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static struct clk_branch spdif_clk = {
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.halt_reg = 0xd4,
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.halt_bit = 1,
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@@ -346,7 +351,9 @@ static struct clk_branch spdif_clk = {
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.enable_mask = BIT(12),
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.hw.init = &(struct clk_init_data){
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.name = "spdif_clk",
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- .parent_names = lcc_spdif_parents,
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+ .parent_hws = (const struct clk_hw*[]){
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+ &spdif_src.clkr.hw,
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+ },
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.num_parents = 1,
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.ops = &clk_branch_ops,
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.flags = CLK_SET_RATE_PARENT,
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@@ -384,8 +391,8 @@ static struct clk_rcg ahbix_clk = {
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.enable_mask = BIT(11),
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.hw.init = &(struct clk_init_data){
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.name = "ahbix",
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- .parent_names = lcc_pxo_pll4,
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- .num_parents = 2,
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+ .parent_data = lcc_pxo_pll4,
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+ .num_parents = ARRAY_SIZE(lcc_pxo_pll4),
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.ops = &clk_rcg_lcc_ops,
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},
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},
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