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3ea6125c50
Currently, the MT7530 DSA subdriver configures the MT7530 switch to provide direct access to switch PHYs, meaning, the switch PHYs listen on the MDIO bus the switch listens on. The PHY muxing feature makes use of this. This is problematic as the PHY may be attached before the switch is initialised, in which case, the PHY will fail to be attached. Since commit 91374ba537bd ("net: dsa: mt7530: support OF-based registration of switch MDIO bus") on mainline Linux, we can describe the switch PHYs on the MDIO bus of the switch on the device tree. When the PHY is described this way, the switch will be initialised first, then the switch MDIO bus will be registered. Only after these steps, the PHY will be attached. Describe the switch PHYs on mt7621.dtsi and remove defining the switch PHY on the SoC's mdio bus node. When the PHY muxing is in use, the interrupts for the muxed PHY won't work, therefore delete the "interrupts" property on the devices where the PHY muxing feature is in use. Signed-off-by: Arınç ÜNAL <arinc.unal@arinc9.com>
200 lines
3.3 KiB
Plaintext
200 lines
3.3 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7621.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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#include <dt-bindings/leds/common.h>
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/ {
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compatible = "raisecom,msg1500-x-00", "mediatek,mt7621-soc";
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model = "RAISECOM MSG1500 X.00";
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aliases {
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led-boot = &led_usb;
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led-failsafe = &led_usb;
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led-upgrade = &led_usb;
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label-mac-device = &gmac0;
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};
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leds {
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compatible = "gpio-leds";
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wlan2g {
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label = "blue:wlan2g";
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gpios = <&gpio 4 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0radio";
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};
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wlan5g {
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label = "blue:wlan5g";
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gpios = <&gpio 3 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1radio";
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};
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led_usb: usb {
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function = LED_FUNCTION_USB;
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color = <LED_COLOR_ID_BLUE>;
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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trigger-sources = <&ehci_port2>;
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linux,default-trigger = "usbport";
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};
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};
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keys {
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compatible = "gpio-keys";
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reset {
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label = "reset";
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RESTART>;
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};
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wps {
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label = "wps";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_WPS_BUTTON>;
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};
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wifi {
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label = "wifi";
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gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
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linux,code = <KEY_RFKILL>;
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};
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};
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};
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&nand {
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status = "okay";
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "Bootloader";
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reg = <0x0 0x80000>;
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read-only;
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};
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partition@80000 {
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label = "Config";
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reg = <0x80000 0x80000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_config_8014: macaddr@8014 {
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compatible = "mac-base";
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reg = <0x8014 0x11>;
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#nvmem-cell-cells = <1>;
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};
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macaddr_config_8036: macaddr@8036 {
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compatible = "mac-base";
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reg = <0x8036 0x11>;
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#nvmem-cell-cells = <1>;
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};
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};
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};
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partition@100000 {
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label = "Factory";
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reg = <0x100000 0x40000>;
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read-only;
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nvmem-layout {
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compatible = "fixed-layout";
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#address-cells = <1>;
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#size-cells = <1>;
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eeprom_factory_0: eeprom@0 {
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reg = <0x0 0x4da8>;
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};
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macaddr_factory_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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};
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};
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partition@140000 {
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label = "kernel";
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reg = <0x140000 0x400000>;
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};
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partition@540000 {
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label = "ubi";
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reg = <0x540000 0x7a40000>;
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};
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};
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,0 {
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compatible = "mediatek,mt76";
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reg = <0x0000 0 0 0 0>;
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/* 5 GHz (phy1) does not take the address from calibration data,
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but setting it manually here works */
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nvmem-cells = <&eeprom_factory_0>, <&macaddr_factory_4>;
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nvmem-cell-names = "eeprom", "mac-address";
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};
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};
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&gmac0 {
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nvmem-cells = <&macaddr_config_8014 0>;
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nvmem-cell-names = "mac-address";
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};
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&gmac1 {
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status = "okay";
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label = "wan";
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phy-handle = <ðphy4>;
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nvmem-cells = <&macaddr_config_8036 0>;
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nvmem-cell-names = "mac-address";
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};
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ðphy4 {
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/delete-property/ interrupts;
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};
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&switch0 {
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ports {
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port@0 {
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status = "okay";
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label = "lan4";
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};
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port@1 {
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status = "okay";
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label = "lan3";
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};
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port@2 {
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status = "okay";
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label = "lan2";
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};
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port@3 {
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status = "okay";
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label = "lan1";
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};
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};
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};
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&state_default {
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gpio {
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groups = "i2c", "jtag", "uart3", "wdt";
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function = "gpio";
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};
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};
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