mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-23 07:22:33 +00:00
df8e6be59a
This adds support for the RTL838x Architecture. SoCs of this type are used in managed and un-managed Switches and Routers with 8-28 ports. Drivers are provided for SoC initialization, GPIOs, Flash, Ethernet including a DSA switch driver and internal and external PHYs used with these switches. Supported SoCs: RTL8380M RTL8381M RTL8382M The kernel will also boot on the following RTL839x SoCs, however driver support apart from spi-nor is missing: RTL8390 RTL8391 RTL8393 The following PHYs are supported: RTL8214FC (Quad QSGMII multiplexing GMAC and SFP port) RTL8218B internal: internal PHY of the RTL838x chips RTL8318b external (QSGMII 8-port GMAC phy) RTL8382M SerDes for 2 SFP ports Initialization sequences for the PHYs are provided in the form of firmware files. Flash driver supports 3 / 4 byte access DSA switch driver supports VLANs, port isolation, STP and port mirroring. The ALLNET ALL-SG8208M is supported as Proof of Concept: RTL8382M SoC 1 MIPS 4KEc core @ 500MHz 8 Internal PHYs (RTL8218B) 128MB DRAM (Nanya NT5TU128MB) 16MB NOR Flash (MXIC 25L128) 8 GBEthernet ports with one green status LED each (SoC controlled) 1 Power LED (not configurable) 1 SYS LED (configurable) 1 On-Off switch (not configurable) 1 Reset button at the right behind right air-vent (not configurable) 1 Reset button on front panel (configurable) 12V 1A barrel connector 1 serial header with populated standard pin connector and with markings GND TX RX Vcc(3.3V), connection properties: 115200 8N1 To install, upload the sysupgrade image to the OEM webpage. Signed-off-by: Birger Koblitz <git@birger-koblitz.de>
42 lines
967 B
Diff
42 lines
967 B
Diff
--- a/drivers/net/phy/phylink.c
|
|
+++ b/drivers/net/phy/phylink.c
|
|
@@ -1244,6 +1244,11 @@
|
|
|
|
/* If we have a PHY, configure the phy */
|
|
if (pl->phydev) {
|
|
+ if (pl->phydev->drv->get_port && pl->phydev->drv->set_port) {
|
|
+ if(pl->phydev->drv->get_port(pl->phydev) != kset->base.port) {
|
|
+ pl->phydev->drv->set_port(pl->phydev, kset->base.port);
|
|
+ }
|
|
+ }
|
|
ret = phy_ethtool_ksettings_set(pl->phydev, &our_kset);
|
|
if (ret)
|
|
return ret;
|
|
@@ -1422,8 +1427,11 @@
|
|
|
|
ASSERT_RTNL();
|
|
|
|
- if (pl->phydev)
|
|
+ if (pl->phydev) {
|
|
+ if (pl->phydev->drv->get_eee)
|
|
+ return pl->phydev->drv->get_eee(pl->phydev, eee);
|
|
ret = phy_ethtool_get_eee(pl->phydev, eee);
|
|
+ }
|
|
|
|
return ret;
|
|
}
|
|
@@ -1440,9 +1448,11 @@
|
|
|
|
ASSERT_RTNL();
|
|
|
|
- if (pl->phydev)
|
|
+ if (pl->phydev) {
|
|
+ if (pl->phydev->drv->set_eee)
|
|
+ return pl->phydev->drv->set_eee(pl->phydev, eee);
|
|
ret = phy_ethtool_set_eee(pl->phydev, eee);
|
|
-
|
|
+ }
|
|
return ret;
|
|
}
|
|
EXPORT_SYMBOL_GPL(phylink_ethtool_set_eee);
|