mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 06:33:41 +00:00
287 lines
7.9 KiB
Diff
287 lines
7.9 KiB
Diff
--- a/arch/arm/kernel/fiq.c
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+++ b/arch/arm/kernel/fiq.c
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@@ -8,6 +8,8 @@
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*
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* FIQ support re-written by Russell King to be more generic
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*
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+ * FIQ handler in C supoprt written by Andy Green <andy@openmoko.com>
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+ *
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* We now properly support a method by which the FIQ handlers can
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* be stacked onto the vector. We still do not support sharing
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* the FIQ vector itself.
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@@ -124,6 +126,83 @@ void __naked get_fiq_regs(struct pt_regs
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: "r" (®s->ARM_r8), "I" (PSR_I_BIT | PSR_F_BIT | FIQ_MODE));
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}
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+/* -------- FIQ handler in C ---------
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+ *
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+ * Major Caveats for using this
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+ * ---------------------------
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+ * *
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+ * * 1) it CANNOT touch any vmalloc()'d memory, only memory
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+ * that was kmalloc()'d. Static allocations in the monolithic kernel
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+ * are kmalloc()'d so they are okay. You can touch memory-mapped IO, but
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+ * the pointer for it has to have been stored in kmalloc'd memory. The
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+ * reason for this is simple: every now and then Linux turns off interrupts
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+ * and reorders the paging tables. If a FIQ happens during this time, the
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+ * virtual memory space can be partly or entirely disordered or missing.
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+ *
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+ * 2) Because vmalloc() is used when a module is inserted, THIS FIQ
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+ * ISR HAS TO BE IN THE MONOLITHIC KERNEL, not a module. But the way
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+ * it is set up, you can all to enable and disable it from your module
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+ * and intercommunicate with it through struct fiq_ipc
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+ * fiq_ipc which you can define in
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+ * asm/archfiq_ipc_type.h. The reason is the same as above, a
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+ * FIQ could happen while even the ISR is not present in virtual memory
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+ * space due to pagetables being changed at the time.
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+ *
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+ * 3) You can't call any Linux API code except simple macros
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+ * - understand that FIQ can come in at any time, no matter what
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+ * state of undress the kernel may privately be in, thinking it
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+ * locked the door by turning off interrupts... FIQ is an
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+ * unstoppable monster force (which is its value)
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+ * - they are not vmalloc()'d memory safe
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+ * - they might do crazy stuff like sleep: FIQ pisses fire and
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+ * is not interested in 'sleep' that the weak seem to need
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+ * - calling APIs from FIQ can re-enter un-renterable things
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+ * - summary: you cannot interoperate with linux APIs directly in the FIQ ISR
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+ *
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+ * If you follow these rules, it is fantastic, an extremely powerful, solid,
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+ * genuine hard realtime feature.
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+ */
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+
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+static void (*current_fiq_c_isr)(void);
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+#define FIQ_C_ISR_STACK_SIZE 256
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+
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+static void __attribute__((naked)) __jump_to_isr(void)
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+{
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+ asm __volatile__ ("mov pc, r8");
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+}
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+
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+
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+static void __attribute__((naked)) __actual_isr(void)
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+{
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+ asm __volatile__ (
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+ "stmdb sp!, {r0-r12, lr};"
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+ "mov fp, sp;"
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+ );
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+
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+ current_fiq_c_isr();
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+
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+ asm __volatile__ (
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+ "ldmia sp!, {r0-r12, lr};"
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+ "subs pc, lr, #4;"
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+ );
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+}
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+
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+void set_fiq_c_handler(void (*isr)(void))
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+{
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+ struct pt_regs regs;
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+
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+ memset(®s, 0, sizeof(regs));
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+ regs.ARM_r8 = (unsigned long) __actual_isr;
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+ regs.ARM_sp = 0xffff001c + FIQ_C_ISR_STACK_SIZE;
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+
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+ set_fiq_handler(__jump_to_isr, 4);
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+
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+ current_fiq_c_isr = isr;
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+
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+ set_fiq_regs(®s);
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+}
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+/* -------- FIQ handler in C ---------*/
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+
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int claim_fiq(struct fiq_handler *f)
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{
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int ret = 0;
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--- a/arch/arm/include/asm/fiq.h
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+++ b/arch/arm/include/asm/fiq.h
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@@ -29,8 +29,9 @@ struct fiq_handler {
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extern int claim_fiq(struct fiq_handler *f);
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extern void release_fiq(struct fiq_handler *f);
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extern void set_fiq_handler(void *start, unsigned int length);
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-extern void set_fiq_regs(struct pt_regs *regs);
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-extern void get_fiq_regs(struct pt_regs *regs);
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+extern void set_fiq_c_handler(void (*handler)(void));
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+extern void __attribute__((naked)) set_fiq_regs(struct pt_regs *regs);
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+extern void __attribute__((naked)) get_fiq_regs(struct pt_regs *regs);
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extern void enable_fiq(int fiq);
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extern void disable_fiq(int fiq);
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--- a/arch/arm/plat-s3c24xx/include/plat/irq.h
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+++ b/arch/arm/plat-s3c24xx/include/plat/irq.h
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@@ -12,6 +12,7 @@
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#include <linux/io.h>
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+#include <mach/irqs.h>
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#include <mach/hardware.h>
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#include <mach/regs-irq.h>
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#include <mach/regs-gpio.h>
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@@ -31,8 +32,15 @@ s3c_irqsub_mask(unsigned int irqno, unsi
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{
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unsigned long mask;
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unsigned long submask;
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ unsigned long flags;
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+#endif
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submask = __raw_readl(S3C2410_INTSUBMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+#endif
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mask = __raw_readl(S3C2410_INTMSK);
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submask |= (1UL << (irqno - IRQ_S3CUART_RX0));
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@@ -45,6 +53,9 @@ s3c_irqsub_mask(unsigned int irqno, unsi
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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+#endif
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}
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@@ -53,8 +64,15 @@ s3c_irqsub_unmask(unsigned int irqno, un
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{
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unsigned long mask;
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unsigned long submask;
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ unsigned long flags;
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+#endif
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submask = __raw_readl(S3C2410_INTSUBMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+#endif
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mask = __raw_readl(S3C2410_INTMSK);
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submask &= ~(1UL << (irqno - IRQ_S3CUART_RX0));
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@@ -63,6 +81,9 @@ s3c_irqsub_unmask(unsigned int irqno, un
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/* write back masks */
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__raw_writel(submask, S3C2410_INTSUBMSK);
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__raw_writel(mask, S3C2410_INTMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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+#endif
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}
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--- a/arch/arm/plat-s3c24xx/irq.c
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+++ b/arch/arm/plat-s3c24xx/irq.c
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@@ -28,6 +28,8 @@
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#include <asm/mach/irq.h>
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#include <plat/regs-irqtype.h>
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+#include <mach/regs-irq.h>
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+#include <mach/regs-gpio.h>
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#include <plat/cpu.h>
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#include <plat/pm.h>
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@@ -37,12 +39,20 @@ static void
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s3c_irq_mask(unsigned int irqno)
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{
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unsigned long mask;
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-
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ unsigned long flags;
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+#endif
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irqno -= IRQ_EINT0;
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-
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+#endif
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mask = __raw_readl(S3C2410_INTMSK);
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mask |= 1UL << irqno;
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__raw_writel(mask, S3C2410_INTMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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+#endif
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}
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static inline void
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@@ -59,9 +69,19 @@ s3c_irq_maskack(unsigned int irqno)
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{
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unsigned long bitval = 1UL << (irqno - IRQ_EINT0);
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unsigned long mask;
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-
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ unsigned long flags;
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+#endif
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+
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+#endif
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mask = __raw_readl(S3C2410_INTMSK);
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__raw_writel(mask|bitval, S3C2410_INTMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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+#endif
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__raw_writel(bitval, S3C2410_SRCPND);
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__raw_writel(bitval, S3C2410_INTPND);
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@@ -72,15 +92,25 @@ static void
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s3c_irq_unmask(unsigned int irqno)
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{
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unsigned long mask;
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ unsigned long flags;
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+#endif
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if (irqno != IRQ_TIMER4 && irqno != IRQ_EINT8t23)
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irqdbf2("s3c_irq_unmask %d\n", irqno);
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irqno -= IRQ_EINT0;
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_save_flags(flags);
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+ local_fiq_disable();
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+#endif
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mask = __raw_readl(S3C2410_INTMSK);
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mask &= ~(1UL << irqno);
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__raw_writel(mask, S3C2410_INTMSK);
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+#ifdef CONFIG_S3C2440_C_FIQ
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+ local_irq_restore(flags);
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+#endif
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}
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struct irq_chip s3c_irq_level_chip = {
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@@ -523,26 +553,26 @@ void __init s3c24xx_init_irq(void)
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last = 0;
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for (i = 0; i < 4; i++) {
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- pend = __raw_readl(S3C2410_INTPND);
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+ pend = __raw_readl(S3C2410_SUBSRCPND);
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if (pend == 0 || pend == last)
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break;
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- __raw_writel(pend, S3C2410_SRCPND);
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- __raw_writel(pend, S3C2410_INTPND);
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- printk("irq: clearing pending status %08x\n", (int)pend);
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+ printk("irq: clearing subpending status %08x\n", (int)pend);
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+ __raw_writel(pend, S3C2410_SUBSRCPND);
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last = pend;
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}
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last = 0;
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for (i = 0; i < 4; i++) {
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- pend = __raw_readl(S3C2410_SUBSRCPND);
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+ pend = __raw_readl(S3C2410_INTPND);
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if (pend == 0 || pend == last)
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break;
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- printk("irq: clearing subpending status %08x\n", (int)pend);
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- __raw_writel(pend, S3C2410_SUBSRCPND);
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+ __raw_writel(pend, S3C2410_SRCPND);
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+ __raw_writel(pend, S3C2410_INTPND);
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+ printk("irq: clearing pending status %08x\n", (int)pend);
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last = pend;
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}
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