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https://github.com/openwrt/openwrt.git
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The patches were generated from the RPi repo with the following command: git format-patch v6.6.34..rpi-6.1.y Some patches needed rebasing and, as usual, the applied and reverted, wireless drivers, Github workflows, READMEs and defconfigs patches were removed. Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
167 lines
5.8 KiB
Diff
167 lines
5.8 KiB
Diff
From d0f6e84d284870eda4a544002eb5ed0dce3d8680 Mon Sep 17 00:00:00 2001
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From: Jonathan Bell <jonathan@raspberrypi.com>
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Date: Mon, 8 Jan 2024 17:10:44 +0000
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Subject: [PATCH 0835/1085] mmc: sdhci-brcmstb: remove 32-bit accessors for
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BCM2712
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The reason for adding these are lost to the mists of time (and for a
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previous chip revision). Removing these accessors appears to have no ill
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effect on production chips, so get rid of the unnecessary RMW cycles.
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Signed-off-by: Jonathan Bell <jonathan@raspberrypi.com>
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---
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drivers/mmc/host/Kconfig | 1 -
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drivers/mmc/host/sdhci-brcmstb.c | 117 -------------------------------
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2 files changed, 118 deletions(-)
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--- a/drivers/mmc/host/Kconfig
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+++ b/drivers/mmc/host/Kconfig
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@@ -1039,7 +1039,6 @@ config MMC_SDHCI_BRCMSTB
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tristate "Broadcom SDIO/SD/MMC support"
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depends on ARCH_BRCMSTB || BMIPS_GENERIC || COMPILE_TEST
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depends on MMC_SDHCI_PLTFM
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- select MMC_SDHCI_IO_ACCESSORS
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select MMC_CQHCI
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select OF_DYNAMIC
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default ARCH_BRCMSTB || BMIPS_GENERIC
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--- a/drivers/mmc/host/sdhci-brcmstb.c
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+++ b/drivers/mmc/host/sdhci-brcmstb.c
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@@ -49,10 +49,6 @@ struct sdhci_brcmstb_priv {
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unsigned int flags;
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struct clk *base_clk;
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u32 base_freq_hz;
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- u32 shadow_cmd;
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- u32 shadow_blk;
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- bool is_cmd_shadowed;
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- bool is_blk_shadowed;
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struct regulator *sde_1v8;
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struct device_node *sde_pcie;
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void *__iomem sde_ioaddr;
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@@ -121,113 +117,6 @@ static void sdhci_brcmstb_set_clock(stru
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sdhci_enable_clk(host, clk);
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}
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-#define REG_OFFSET_IN_BITS(reg) ((reg) << 3 & 0x18)
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-
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-static inline u32 sdhci_brcmstb_32only_readl(struct sdhci_host *host, int reg)
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-{
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- u32 val = readl(host->ioaddr + reg);
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-
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- pr_debug("%s: readl [0x%02x] 0x%08x\n",
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- mmc_hostname(host->mmc), reg, val);
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- return val;
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-}
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-
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-static u16 sdhci_brcmstb_32only_readw(struct sdhci_host *host, int reg)
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-{
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- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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- struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
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- u32 val;
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- u16 word;
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-
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- if ((reg == SDHCI_TRANSFER_MODE) && brcmstb_priv->is_cmd_shadowed) {
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- /* Get the saved transfer mode */
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- val = brcmstb_priv->shadow_cmd;
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- } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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- brcmstb_priv->is_blk_shadowed) {
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- /* Get the saved block info */
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- val = brcmstb_priv->shadow_blk;
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- } else {
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- val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
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- }
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- word = val >> REG_OFFSET_IN_BITS(reg) & 0xffff;
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- return word;
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-}
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-
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-static u8 sdhci_brcmstb_32only_readb(struct sdhci_host *host, int reg)
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-{
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- u32 val = sdhci_brcmstb_32only_readl(host, (reg & ~3));
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- u8 byte = val >> REG_OFFSET_IN_BITS(reg) & 0xff;
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- return byte;
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-}
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-
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-static inline void sdhci_brcmstb_32only_writel(struct sdhci_host *host, u32 val, int reg)
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-{
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- pr_debug("%s: writel [0x%02x] 0x%08x\n",
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- mmc_hostname(host->mmc), reg, val);
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-
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- writel(val, host->ioaddr + reg);
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-}
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-
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-/*
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- * BCM2712 unfortunately carries with it a perennial bug with the SD controller
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- * register interface present on previous chips (2711/2709/2708). Accesses must
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- * be dword-sized and a read-modify-write cycle to the 32-bit registers
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- * containing the COMMAND, TRANSFER_MODE, BLOCK_SIZE and BLOCK_COUNT registers
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- * tramples the upper/lower 16 bits of data written. BCM2712 does not seem to
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- * need the extreme delay between each write as on previous chips, just the
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- * serialisation of writes to these registers in a single 32-bit operation.
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- */
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-static void sdhci_brcmstb_32only_writew(struct sdhci_host *host, u16 val, int reg)
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-{
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- struct sdhci_pltfm_host *pltfm_host = sdhci_priv(host);
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- struct sdhci_brcmstb_priv *brcmstb_priv = sdhci_pltfm_priv(pltfm_host);
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- u32 word_shift = REG_OFFSET_IN_BITS(reg);
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- u32 mask = 0xffff << word_shift;
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- u32 oldval, newval;
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-
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- if (reg == SDHCI_COMMAND) {
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- /* Write the block now as we are issuing a command */
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- if (brcmstb_priv->is_blk_shadowed) {
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- sdhci_brcmstb_32only_writel(host, brcmstb_priv->shadow_blk,
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- SDHCI_BLOCK_SIZE);
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- brcmstb_priv->is_blk_shadowed = false;
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- }
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- oldval = brcmstb_priv->shadow_cmd;
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- brcmstb_priv->is_cmd_shadowed = false;
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- } else if ((reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) &&
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- brcmstb_priv->is_blk_shadowed) {
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- /* Block size and count are stored in shadow reg */
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- oldval = brcmstb_priv->shadow_blk;
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- } else {
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- /* Read reg, all other registers are not shadowed */
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- oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
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- }
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- newval = (oldval & ~mask) | (val << word_shift);
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-
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- if (reg == SDHCI_TRANSFER_MODE) {
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- /* Save the transfer mode until the command is issued */
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- brcmstb_priv->shadow_cmd = newval;
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- brcmstb_priv->is_cmd_shadowed = true;
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- } else if (reg == SDHCI_BLOCK_SIZE || reg == SDHCI_BLOCK_COUNT) {
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- /* Save the block info until the command is issued */
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- brcmstb_priv->shadow_blk = newval;
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- brcmstb_priv->is_blk_shadowed = true;
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- } else {
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- /* Command or other regular 32-bit write */
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- sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
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- }
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-}
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-
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-static void sdhci_brcmstb_32only_writeb(struct sdhci_host *host, u8 val, int reg)
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-{
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- u32 oldval = sdhci_brcmstb_32only_readl(host, (reg & ~3));
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- u32 byte_shift = REG_OFFSET_IN_BITS(reg);
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- u32 mask = 0xff << byte_shift;
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- u32 newval = (oldval & ~mask) | (val << byte_shift);
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-
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- sdhci_brcmstb_32only_writel(host, newval, reg & ~3);
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-}
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-
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static void sdhci_brcmstb_set_power(struct sdhci_host *host, unsigned char mode,
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unsigned short vdd)
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{
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@@ -441,12 +330,6 @@ static struct sdhci_ops sdhci_brcmstb_op
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};
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static struct sdhci_ops sdhci_brcmstb_ops_2712 = {
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- .read_l = sdhci_brcmstb_32only_readl,
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- .read_w = sdhci_brcmstb_32only_readw,
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- .read_b = sdhci_brcmstb_32only_readb,
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- .write_l = sdhci_brcmstb_32only_writel,
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- .write_w = sdhci_brcmstb_32only_writew,
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- .write_b = sdhci_brcmstb_32only_writeb,
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.set_clock = sdhci_set_clock,
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.set_power = sdhci_brcmstb_set_power,
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.set_bus_width = sdhci_set_bus_width,
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