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c22c63bce3
Hardware -------- RockChip RK3566 ARM64 (4 cores) - up to 8GB LPDDR4X - 1x HDMI, - 2x MIPI DSI - 2x MIPI CSI2 - 1x eDP - 1x PCIe card - 2x SATA - 2x USB 2.0 Host - 1x USB 3.0 - 1x USB 2.0 OTG - 10/100/1000 Base-T - microSD slot - 40-pin GPIO expansion header - 12V DC Radxa CM3 needs to mount on top of this IO board in order to create complete Radxa CM3 IO board platform. Installation ------------ Uncompress the OpenWrt sysupgrade and write it to a micro SD card or internal eMMC using dd. Reviewed-by: Tianling Shen <cnsztl@immortalwrt.org> Signed-off-by: Marius Durbaca <mariusd84@gmail.com>
132 lines
3.5 KiB
Diff
132 lines
3.5 KiB
Diff
From cc52bfc04726a574fc4440bbbe0c710890e7040a Mon Sep 17 00:00:00 2001
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From: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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Date: Wed, 25 Jan 2023 21:40:22 +0530
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Subject: [PATCH] arm64: dts: rockchip: Enable Ethernet for Radxa CM3 IO
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Add ethernet nodes for enabling gmac1 on the Radxa CM3 IO board.
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Signed-off-by: Manoj Sai <abbaraju.manojsai@amarulasolutions.com>
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Link: https://lore.kernel.org/r/20230125161023.12115-1-jagan@amarulasolutions.com
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Signed-off-by: Heiko Stuebner <heiko@sntech.de>
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---
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.../boot/dts/rockchip/rk3566-radxa-cm3-io.dts | 93 +++++++++++++++++++
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1 file changed, 93 insertions(+)
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--- a/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
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+++ b/arch/arm64/boot/dts/rockchip/rk3566-radxa-cm3-io.dts
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@@ -21,6 +21,13 @@
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stdout-path = "serial2:1500000n8";
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};
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+ gmac1_clkin: external-gmac1-clock {
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+ compatible = "fixed-clock";
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+ clock-frequency = <125000000>;
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+ clock-output-names = "gmac1_clkin";
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+ #clock-cells = <0>;
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+ };
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+
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hdmi-con {
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compatible = "hdmi-connector";
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type = "a";
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@@ -83,6 +90,29 @@
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status = "okay";
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};
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+&gmac1 {
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+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1>;
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+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&gmac1_clkin>;
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+ assigned-clock-rates = <0>, <125000000>;
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+ clock_in_out = "input";
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+ phy-handle = <&rgmii_phy1>;
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+ phy-mode = "rgmii";
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+ pinctrl-names = "default";
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+ pinctrl-0 = <&gmac1m0_miim
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+ &gmac1m0_tx_bus2
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+ &gmac1m0_rx_bus2
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+ &gmac1m0_rgmii_clk
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+ &gmac1m0_rgmii_bus
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+ &gmac1m0_clkinout>;
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+ snps,reset-gpio = <&gpio4 RK_PC2 GPIO_ACTIVE_LOW>;
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+ snps,reset-active-low;
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+ /* Reset time is 20ms, 100ms for rtl8211f */
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+ snps,reset-delays-us = <0 20000 100000>;
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+ tx_delay = <0x46>;
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+ rx_delay = <0x2e>;
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+ status = "okay";
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+};
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+
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&hdmi {
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avdd-0v9-supply = <&vdda0v9_image>;
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avdd-1v8-supply = <&vcca1v8_image>;
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@@ -105,7 +135,70 @@
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status = "okay";
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};
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+&mdio1 {
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+ rgmii_phy1: ethernet-phy@0 {
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+ compatible="ethernet-phy-ieee802.3-c22";
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+ reg= <0x0>;
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+ };
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+};
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+
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&pinctrl {
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+ gmac1 {
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+ gmac1m0_miim: gmac1m0-miim {
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+ rockchip,pins =
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+ /* gmac1_mdcm0 */
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+ <3 RK_PC4 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_mdiom0 */
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+ <3 RK_PC5 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+
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+ gmac1m0_rx_bus2: gmac1m0-rx-bus2 {
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+ rockchip,pins =
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+ /* gmac1_rxd0m0 */
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+ <3 RK_PB1 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_rxd1m0 */
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+ <3 RK_PB2 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_rxdvcrsm0 */
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+ <3 RK_PB3 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+
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+ gmac1m0_tx_bus2: gmac1m0-tx-bus2 {
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+ rockchip,pins =
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+ /* gmac1_txd0m0 */
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+ <3 RK_PB5 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_txd1m0 */
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+ <3 RK_PB6 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_txenm0 */
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+ <3 RK_PB7 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+
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+ gmac1m0_rgmii_clk: gmac1m0-rgmii-clk {
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+ rockchip,pins =
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+ /* gmac1_rxclkm0 */
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+ <3 RK_PA7 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_txclkm0 */
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+ <3 RK_PA6 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+
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+ gmac1m0_rgmii_bus: gmac1m0-rgmii-bus {
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+ rockchip,pins =
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+ /* gmac1_rxd2m0 */
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+ <3 RK_PA4 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_rxd3m0 */
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+ <3 RK_PA5 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_txd2m0 */
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+ <3 RK_PA2 3 &pcfg_pull_none_drv_level_15>,
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+ /* gmac1_txd3m0 */
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+ <3 RK_PA3 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+
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+ gmac1m0_clkinout: gmac1m0-clkinout {
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+ rockchip,pins =
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+ /* gmac1_mclkinoutm0 */
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+ <3 RK_PC0 3 &pcfg_pull_none_drv_level_15>;
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+ };
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+ };
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+
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leds {
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pi_nled_activity: pi-nled-activity {
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rockchip,pins = <4 RK_PA4 RK_FUNC_GPIO &pcfg_pull_none>;
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