mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 10:08:59 +00:00
b04f245c39
Changelog: https://cdn.kernel.org/pub/linux/kernel/v6.x/ChangeLog-6.6.23 Removed upstreamed: pending-6.6/735-net-mediatek-mtk_eth_soc-release-MAC_MCR_FORCE_LINK-.patch[1] pending-6.6/736-net-ethernet-mtk_eth_soc-fix-PPE-hanging-issue.patch[2] mediatek/patches-6.6/232-clk-mediatek-mt7981-topckgen-flag-SGM_REG_SEL-as-cri.patch[3] Manually rebased: mediatek/patches-6.6/100-dts-update-mt7622-rfb1.patch Added: generic/backports-6.6/981-mtd-spinand-Add-support-for-5-byte-IDs.patch[4] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=1f32abb474c1c9bdb21d9eda74c325a0b3a162e5 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=943c14ece95eb1cf98d477462aebcbfdfd714633 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v6.6.23&id=6ff01b314149d1cf59caebc29384f0beed21cba4 4. See comments in https://github.com/openwrt/openwrt/pull/14992 regarding broken flogic/xiaomi_redmi-router-ax6000-ubootmod Build system: x86/64 Build-tested: x86/64/AMD Cezanne, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Run-tested: x86/64/AMD Cezannei, flogic/xiaomi_redmi-router-ax6000-ubootmod, flogic/glinet_gl-mt6000 Signed-off-by: John Audia <therealgraysky@proton.me>
92 lines
2.9 KiB
Diff
92 lines
2.9 KiB
Diff
From 9924e9b91b43aaa1610a1d59c4caa43785948cf6 Mon Sep 17 00:00:00 2001
|
|
From: Frank Wunderlich <frank-w@public-files.de>
|
|
Date: Fri, 22 Sep 2023 07:50:20 +0200
|
|
Subject: [PATCH 37/42] thermal/drivers/mediatek/lvts_thermal: Add mt7988
|
|
support
|
|
|
|
Add Support for Mediatek Filogic 880/MT7988 LVTS.
|
|
|
|
Signed-off-by: Frank Wunderlich <frank-w@public-files.de>
|
|
Tested-by: Daniel Golle <daniel@makrotopia.org>
|
|
Signed-off-by: Daniel Lezcano <daniel.lezcano@linaro.org>
|
|
Link: https://lore.kernel.org/r/20230922055020.6436-5-linux@fw-web.de
|
|
---
|
|
drivers/thermal/mediatek/lvts_thermal.c | 38 +++++++++++++++++++++++++
|
|
1 file changed, 38 insertions(+)
|
|
|
|
--- a/drivers/thermal/mediatek/lvts_thermal.c
|
|
+++ b/drivers/thermal/mediatek/lvts_thermal.c
|
|
@@ -82,6 +82,8 @@
|
|
#define LVTS_GOLDEN_TEMP_DEFAULT 50
|
|
#define LVTS_COEFF_A_MT8195 -250460
|
|
#define LVTS_COEFF_B_MT8195 250460
|
|
+#define LVTS_COEFF_A_MT7988 -204650
|
|
+#define LVTS_COEFF_B_MT7988 204650
|
|
|
|
#define LVTS_MSR_IMMEDIATE_MODE 0
|
|
#define LVTS_MSR_FILTERED_MODE 1
|
|
@@ -89,6 +91,7 @@
|
|
#define LVTS_MSR_READ_TIMEOUT_US 400
|
|
#define LVTS_MSR_READ_WAIT_US (LVTS_MSR_READ_TIMEOUT_US / 2)
|
|
|
|
+#define LVTS_HW_SHUTDOWN_MT7988 105000
|
|
#define LVTS_HW_SHUTDOWN_MT8195 105000
|
|
|
|
#define LVTS_MINIMUM_THRESHOLD 20000
|
|
@@ -1269,6 +1272,33 @@ static void lvts_remove(struct platform_
|
|
lvts_debugfs_exit(lvts_td);
|
|
}
|
|
|
|
+static const struct lvts_ctrl_data mt7988_lvts_ap_data_ctrl[] = {
|
|
+ {
|
|
+ .cal_offset = { 0x00, 0x04, 0x08, 0x0c },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT7988_CPU_0 },
|
|
+ { .dt_id = MT7988_CPU_1 },
|
|
+ { .dt_id = MT7988_ETH2P5G_0 },
|
|
+ { .dt_id = MT7988_ETH2P5G_1 }
|
|
+ },
|
|
+ .num_lvts_sensor = 4,
|
|
+ .offset = 0x0,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
|
|
+ },
|
|
+ {
|
|
+ .cal_offset = { 0x14, 0x18, 0x1c, 0x20 },
|
|
+ .lvts_sensor = {
|
|
+ { .dt_id = MT7988_TOPS_0},
|
|
+ { .dt_id = MT7988_TOPS_1},
|
|
+ { .dt_id = MT7988_ETHWARP_0},
|
|
+ { .dt_id = MT7988_ETHWARP_1}
|
|
+ },
|
|
+ .num_lvts_sensor = 4,
|
|
+ .offset = 0x100,
|
|
+ .hw_tshut_temp = LVTS_HW_SHUTDOWN_MT7988,
|
|
+ }
|
|
+};
|
|
+
|
|
static const struct lvts_ctrl_data mt8195_lvts_mcu_data_ctrl[] = {
|
|
{
|
|
.cal_offset = { 0x04, 0x07 },
|
|
@@ -1348,6 +1378,13 @@ static const struct lvts_ctrl_data mt819
|
|
}
|
|
};
|
|
|
|
+static const struct lvts_data mt7988_lvts_ap_data = {
|
|
+ .lvts_ctrl = mt7988_lvts_ap_data_ctrl,
|
|
+ .num_lvts_ctrl = ARRAY_SIZE(mt7988_lvts_ap_data_ctrl),
|
|
+ .temp_factor = LVTS_COEFF_A_MT7988,
|
|
+ .temp_offset = LVTS_COEFF_B_MT7988,
|
|
+};
|
|
+
|
|
static const struct lvts_data mt8195_lvts_mcu_data = {
|
|
.lvts_ctrl = mt8195_lvts_mcu_data_ctrl,
|
|
.num_lvts_ctrl = ARRAY_SIZE(mt8195_lvts_mcu_data_ctrl),
|
|
@@ -1363,6 +1400,7 @@ static const struct lvts_data mt8195_lvt
|
|
};
|
|
|
|
static const struct of_device_id lvts_of_match[] = {
|
|
+ { .compatible = "mediatek,mt7988-lvts-ap", .data = &mt7988_lvts_ap_data },
|
|
{ .compatible = "mediatek,mt8195-lvts-mcu", .data = &mt8195_lvts_mcu_data },
|
|
{ .compatible = "mediatek,mt8195-lvts-ap", .data = &mt8195_lvts_ap_data },
|
|
{},
|