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41ba4b04c8
add fixes for * ethernet * cpufreq * nand * a7-timer Signed-off-by: John Crispin <blogic@openwrt.org> SVN-Revision: 49098
100 lines
3.5 KiB
Diff
100 lines
3.5 KiB
Diff
From 8d134cbe750b59d15c591622d81e2e9daa09f0c4 Mon Sep 17 00:00:00 2001
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From: Shunli Wang <shunli.wang@mediatek.com>
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Date: Tue, 5 Jan 2016 14:30:21 +0800
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Subject: [PATCH 10/78] reset: mediatek: mt2701 reset controller dt-binding
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file
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Dt-binding file about reset controller is used to provide
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kinds of definition, which is referenced by dts file and
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IC-specified reset controller driver code.
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Signed-off-by: Shunli Wang <shunli.wang@mediatek.com>
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---
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.../dt-bindings/reset-controller/mt2701-resets.h | 74 ++++++++++++++++++++
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1 file changed, 74 insertions(+)
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create mode 100644 include/dt-bindings/reset-controller/mt2701-resets.h
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diff --git a/include/dt-bindings/reset-controller/mt2701-resets.h b/include/dt-bindings/reset-controller/mt2701-resets.h
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new file mode 100644
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index 0000000..00efeb0
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--- /dev/null
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+++ b/include/dt-bindings/reset-controller/mt2701-resets.h
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@@ -0,0 +1,74 @@
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+/*
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+ * Copyright (c) 2015 MediaTek, Shunli Wang <shunli.wang@mediatek.com>
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+ *
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+ * This program is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ * This program is distributed in the hope that it will be useful,
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+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
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+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
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+ * GNU General Public License for more details.
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+ */
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+
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+#ifndef _DT_BINDINGS_RESET_CONTROLLER_MT2701
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+#define _DT_BINDINGS_RESET_CONTROLLER_MT2701
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+
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+/* INFRACFG resets */
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+#define MT2701_INFRA_EMI_REG_RST 0
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+#define MT2701_INFRA_DRAMC0_A0_RST 1
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+#define MT2701_INFRA_FHCTL_RST 2
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+#define MT2701_INFRA_APCIRQ_EINT_RST 3
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+#define MT2701_INFRA_APXGPT_RST 4
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+#define MT2701_INFRA_SCPSYS_RST 5
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+#define MT2701_INFRA_KP_RST 6
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+#define MT2701_INFRA_PMIC_WRAP_RST 7
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+#define MT2701_INFRA_MIPI_RST 8
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+#define MT2701_INFRA_IRRX_RST 9
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+#define MT2701_INFRA_CEC_RST 10
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+#define MT2701_INFRA_EMI_RST 32
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+#define MT2701_INFRA_DRAMC0_RST 34
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+#define MT2701_INFRA_TRNG_RST 37
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+#define MT2701_INFRA_SYSIRQ_RST 38
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+
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+/* PERICFG resets */
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+#define MT2701_PERI_UART0_SW_RST 0
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+#define MT2701_PERI_UART1_SW_RST 1
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+#define MT2701_PERI_UART2_SW_RST 2
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+#define MT2701_PERI_UART3_SW_RST 3
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+#define MT2701_PERI_GCPU_SW_RST 5
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+#define MT2701_PERI_BTIF_SW_RST 6
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+#define MT2701_PERI_PWM_SW_RST 8
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+#define MT2701_PERI_AUXADC_SW_RST 10
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+#define MT2701_PERI_DMA_SW_RST 11
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+#define MT2701_PERI_NFI_SW_RST 14
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+#define MT2701_PERI_NLI_SW_RST 15
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+#define MT2701_PERI_THERM_SW_RST 16
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+#define MT2701_PERI_MSDC2_SW_RST 17
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+#define MT2701_PERI_MSDC0_SW_RST 19
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+#define MT2701_PERI_MSDC1_SW_RST 20
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+#define MT2701_PERI_I2C0_SW_RST 22
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+#define MT2701_PERI_I2C1_SW_RST 23
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+#define MT2701_PERI_I2C2_SW_RST 24
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+#define MT2701_PERI_I2C3_SW_RST 25
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+#define MT2701_PERI_USB_SW_RST 28
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+#define MT2701_PERI_ETH_SW_RST 29
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+#define MT2701_PERI_SPI0_SW_RST 33
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+
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+/* TOPRGU resets */
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+#define MT2701_TOPRGU_INFRA_RST 0
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+#define MT2701_TOPRGU_MM_RST 1
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+#define MT2701_TOPRGU_MFG_RST 2
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+#define MT2701_TOPRGU_ETHDMA_RST 3
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+#define MT2701_TOPRGU_VDEC_RST 4
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+#define MT2701_TOPRGU_VENC_IMG_RST 5
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+#define MT2701_TOPRGU_DDRPHY_RST 6
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+#define MT2701_TOPRGU_MD_RST 7
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+#define MT2701_TOPRGU_INFRA_AO_RST 8
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+#define MT2701_TOPRGU_CONN_RST 9
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+#define MT2701_TOPRGU_APMIXED_RST 10
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+#define MT2701_TOPRGU_HIFSYS_RST 11
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+#define MT2701_TOPRGU_CONN_MCU_RST 12
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+#define MT2701_TOPRGU_BDP_DISP_RST 13
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+
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+#endif /* _DT_BINDINGS_RESET_CONTROLLER_MT2701 */
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--
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1.7.10.4
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