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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64)
45 lines
1.5 KiB
Diff
45 lines
1.5 KiB
Diff
From 2c241c25b76d105f798881e1a3c6e3c09c3b27ff Mon Sep 17 00:00:00 2001
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From: Maxime Ripard <maxime@cerno.tech>
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Date: Mon, 13 Jan 2020 13:40:37 +0100
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Subject: [PATCH] drm/vc4: crtc: Add function to compute FIFO level
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bits
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The longer FIFOs in vc5 pixelvalves means that the FIFO full level
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doesn't fit in the original register field and that we also have a
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secondary field. In order to prepare for this, let's move the registers
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fill part to a helper function.
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Signed-off-by: Maxime Ripard <maxime@cerno.tech>
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---
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drivers/gpu/drm/vc4/vc4_crtc.c | 11 +++++++++--
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1 file changed, 9 insertions(+), 2 deletions(-)
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--- a/drivers/gpu/drm/vc4/vc4_crtc.c
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+++ b/drivers/gpu/drm/vc4/vc4_crtc.c
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@@ -277,6 +277,14 @@ static u32 vc4_get_fifo_full_level(struc
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}
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}
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+static u32 vc4_crtc_get_fifo_full_level_bits(struct vc4_crtc *vc4_crtc,
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+ u32 format)
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+{
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+ u32 level = vc4_get_fifo_full_level(vc4_crtc, format);
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+ return VC4_SET_FIELD(level & 0x3f,
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+ PV_CONTROL_FIFO_LEVEL);
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+}
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+
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/*
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* Returns the encoder attached to the CRTC.
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*
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@@ -377,9 +385,8 @@ static void vc4_crtc_config_pv(struct dr
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CRTC_WRITE(PV_HACT_ACT, mode->hdisplay * pixel_rep);
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CRTC_WRITE(PV_CONTROL,
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+ vc4_crtc_get_fifo_full_level_bits(vc4_crtc, format) |
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VC4_SET_FIELD(format, PV_CONTROL_FORMAT) |
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- VC4_SET_FIELD(vc4_get_fifo_full_level(vc4_crtc, format),
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- PV_CONTROL_FIFO_LEVEL) |
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VC4_SET_FIELD(pixel_rep - 1, PV_CONTROL_PIXEL_REP) |
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PV_CONTROL_CLR_AT_START |
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PV_CONTROL_TRIGGER_UNDERFLOW |
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