openwrt/target/linux/mediatek/patches-6.6/259-clk-mediatek-mt2701-mm-add-missing-dummy-clk.patch
Daniel Golle f71ce1c34e
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mediatek: add pending patches fixing video output on MT7623N
Add a bunch of fixes for HDMI output and Mali-450 GPU rendering on
MT7623N, ie. the BananaPi R2.

Signed-off-by: Daniel Golle <daniel@makrotopia.org>
2024-12-16 00:46:38 +00:00

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From patchwork Sun Dec 15 22:14:34 2024
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X-Patchwork-Submitter: Daniel Golle <daniel@makrotopia.org>
X-Patchwork-Id: 13909008
Date: Sun, 15 Dec 2024 22:14:34 +0000
From: Daniel Golle <daniel@makrotopia.org>
To: Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Matthias Brugger <matthias.bgg@gmail.com>,
AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>,
Alexandre Mergnat <amergnat@baylibre.com>,
Geert Uytterhoeven <geert+renesas@glider.be>,
Daniel Golle <daniel@makrotopia.org>,
Uwe =?iso-8859-1?q?Kleine-K=F6nig?= <u.kleine-koenig@baylibre.com>,
Miles Chen <miles.chen@mediatek.com>, Chen-Yu Tsai <wenst@chromium.org>,
Frank Wunderlich <frank-w@public-files.de>, John Crispin <john@phrozen.org>,
linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org,
linux-arm-kernel@lists.infradead.org, linux-mediatek@lists.infradead.org,
stable@vger.kernel.org
Subject: [PATCH 4/5] clk: mediatek: mt2701-mm: add missing dummy clk
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<9de23440fcba1ffef9e77d58c9f505105e57a250.1734300668.git.daniel@makrotopia.org>
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Add dummy clk which was missed during the conversion to
mtk_clk_pdev_probe() and is required for the existing DT bindings to
keep working.
Fixes: 65c10c50c9c7 ("clk: mediatek: Migrate to mtk_clk_pdev_probe() for multimedia clocks")
Cc: stable@vger.kernel.org
Signed-off-by: Daniel Golle <daniel@makrotopia.org>
---
drivers/clk/mediatek/clk-mt2701-mm.c | 1 +
1 file changed, 1 insertion(+)
--- a/drivers/clk/mediatek/clk-mt2701-mm.c
+++ b/drivers/clk/mediatek/clk-mt2701-mm.c
@@ -31,6 +31,7 @@ static const struct mtk_gate_regs disp1_
GATE_MTK(_id, _name, _parent, &disp1_cg_regs, _shift, &mtk_clk_gate_ops_setclr)
static const struct mtk_gate mm_clks[] = {
+ GATE_DUMMY(CLK_DUMMY, "mm_dummy"),
GATE_DISP0(CLK_MM_SMI_COMMON, "mm_smi_comm", "mm_sel", 0),
GATE_DISP0(CLK_MM_SMI_LARB0, "mm_smi_larb0", "mm_sel", 1),
GATE_DISP0(CLK_MM_CMDQ, "mm_cmdq", "mm_sel", 2),