mirror of
https://github.com/openwrt/openwrt.git
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595 lines
15 KiB
Diff
595 lines
15 KiB
Diff
--- a/drivers/mtd/devices/Kconfig
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+++ b/drivers/mtd/devices/Kconfig
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@@ -120,6 +120,10 @@ config MTD_BCM47XXSFLASH
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registered by bcma as platform devices. This enables driver for
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serial flash memories (only read-only mode is implemented).
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+config MTD_AR2315
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+ tristate "Atheros AR2315+ SPI Flash support"
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+ depends on SOC_AR2315
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+
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config MTD_SLRAM
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tristate "Uncached system RAM"
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help
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--- a/drivers/mtd/devices/Makefile
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+++ b/drivers/mtd/devices/Makefile
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@@ -14,6 +14,7 @@ obj-$(CONFIG_MTD_DATAFLASH) += mtd_dataf
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obj-$(CONFIG_MTD_M25P80) += m25p80.o
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obj-$(CONFIG_MTD_SPEAR_SMI) += spear_smi.o
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obj-$(CONFIG_MTD_SST25L) += sst25l.o
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+obj-$(CONFIG_MTD_AR2315) += ar2315.o
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obj-$(CONFIG_MTD_BCM47XXSFLASH) += bcm47xxsflash.o
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obj-$(CONFIG_MTD_ST_SPI_FSM) += st_spi_fsm.o
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--- /dev/null
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+++ b/drivers/mtd/devices/ar2315.c
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@@ -0,0 +1,459 @@
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+
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+/*
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+ * MTD driver for the SPI Flash Memory support on Atheros AR2315
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+ *
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+ * Copyright (c) 2005-2006 Atheros Communications Inc.
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+ * Copyright (C) 2006-2007 FON Technology, SL.
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+ * Copyright (C) 2006-2007 Imre Kaloz <kaloz@openwrt.org>
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+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
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+ * Copyright (C) 2012 Alexandros C. Couloumbis <alex@ozo.com>
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+ *
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+ * This code is free software; you can redistribute it and/or modify
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+ * it under the terms of the GNU General Public License version 2 as
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+ * published by the Free Software Foundation.
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+ *
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+ */
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+
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+#include <linux/kernel.h>
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+#include <linux/module.h>
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+#include <linux/types.h>
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+#include <linux/errno.h>
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+#include <linux/slab.h>
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+#include <linux/mtd/mtd.h>
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+#include <linux/mtd/partitions.h>
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+#include <linux/platform_device.h>
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+#include <linux/sched.h>
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+#include <linux/delay.h>
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+#include <linux/io.h>
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+#include <linux/mutex.h>
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+
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+#include "ar2315_spiflash.h"
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+
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+#define DRIVER_NAME "ar2315-spiflash"
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+
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+#define busy_wait(_priv, _condition, _wait) do { \
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+ while (_condition) { \
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+ if (_wait > 1) \
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+ msleep(_wait); \
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+ else if ((_wait == 1) && need_resched()) \
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+ schedule(); \
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+ else \
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+ udelay(1); \
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+ } \
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+} while (0)
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+
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+enum {
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+ FLASH_NONE,
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+ FLASH_1MB,
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+ FLASH_2MB,
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+ FLASH_4MB,
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+ FLASH_8MB,
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+ FLASH_16MB,
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+};
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+
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+/* Flash configuration table */
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+struct flashconfig {
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+ u32 byte_cnt;
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+ u32 sector_cnt;
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+ u32 sector_size;
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+};
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+
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+static const struct flashconfig flashconfig_tbl[] = {
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+ [FLASH_NONE] = { 0, 0, 0},
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+ [FLASH_1MB] = { STM_1MB_BYTE_COUNT, STM_1MB_SECTOR_COUNT,
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+ STM_1MB_SECTOR_SIZE},
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+ [FLASH_2MB] = { STM_2MB_BYTE_COUNT, STM_2MB_SECTOR_COUNT,
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+ STM_2MB_SECTOR_SIZE},
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+ [FLASH_4MB] = { STM_4MB_BYTE_COUNT, STM_4MB_SECTOR_COUNT,
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+ STM_4MB_SECTOR_SIZE},
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+ [FLASH_8MB] = { STM_8MB_BYTE_COUNT, STM_8MB_SECTOR_COUNT,
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+ STM_8MB_SECTOR_SIZE},
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+ [FLASH_16MB] = { STM_16MB_BYTE_COUNT, STM_16MB_SECTOR_COUNT,
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+ STM_16MB_SECTOR_SIZE}
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+};
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+
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+/* Mapping of generic opcodes to STM serial flash opcodes */
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+enum {
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+ SPI_WRITE_ENABLE,
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+ SPI_WRITE_DISABLE,
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+ SPI_RD_STATUS,
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+ SPI_WR_STATUS,
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+ SPI_RD_DATA,
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+ SPI_FAST_RD_DATA,
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+ SPI_PAGE_PROGRAM,
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+ SPI_SECTOR_ERASE,
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+ SPI_BULK_ERASE,
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+ SPI_DEEP_PWRDOWN,
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+ SPI_RD_SIG,
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+};
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+
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+struct opcodes {
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+ __u16 code;
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+ __s8 tx_cnt;
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+ __s8 rx_cnt;
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+};
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+
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+static const struct opcodes stm_opcodes[] = {
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+ [SPI_WRITE_ENABLE] = {STM_OP_WR_ENABLE, 1, 0},
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+ [SPI_WRITE_DISABLE] = {STM_OP_WR_DISABLE, 1, 0},
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+ [SPI_RD_STATUS] = {STM_OP_RD_STATUS, 1, 1},
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+ [SPI_WR_STATUS] = {STM_OP_WR_STATUS, 1, 0},
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+ [SPI_RD_DATA] = {STM_OP_RD_DATA, 4, 4},
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+ [SPI_FAST_RD_DATA] = {STM_OP_FAST_RD_DATA, 5, 0},
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+ [SPI_PAGE_PROGRAM] = {STM_OP_PAGE_PGRM, 8, 0},
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+ [SPI_SECTOR_ERASE] = {STM_OP_SECTOR_ERASE, 4, 0},
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+ [SPI_BULK_ERASE] = {STM_OP_BULK_ERASE, 1, 0},
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+ [SPI_DEEP_PWRDOWN] = {STM_OP_DEEP_PWRDOWN, 1, 0},
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+ [SPI_RD_SIG] = {STM_OP_RD_SIG, 4, 1},
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+};
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+
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+/* Driver private data structure */
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+struct spiflash_priv {
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+ struct mtd_info mtd;
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+ void __iomem *readaddr; /* memory mapped data for read */
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+ void __iomem *mmraddr; /* memory mapped register space */
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+ struct mutex lock; /* serialize registers access */
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+};
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+
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+#define to_spiflash(_mtd) container_of(_mtd, struct spiflash_priv, mtd)
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+
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+enum {
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+ FL_READY,
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+ FL_READING,
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+ FL_ERASING,
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+ FL_WRITING
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+};
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+
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+/*****************************************************************************/
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+
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+static u32
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+spiflash_read_reg(struct spiflash_priv *priv, int reg)
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+{
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+ return ioread32(priv->mmraddr + reg);
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+}
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+
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+static void
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+spiflash_write_reg(struct spiflash_priv *priv, int reg, u32 data)
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+{
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+ iowrite32(data, priv->mmraddr + reg);
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+}
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+
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+static u32
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+spiflash_wait_busy(struct spiflash_priv *priv)
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+{
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+ u32 reg;
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+
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+ busy_wait(priv, (reg = spiflash_read_reg(priv, SPI_FLASH_CTL)) &
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+ SPI_CTL_BUSY, 0);
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+ return reg;
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+}
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+
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+static u32
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+spiflash_sendcmd(struct spiflash_priv *priv, int opcode, u32 addr)
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+{
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+ const struct opcodes *op;
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+ u32 reg, mask;
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+
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+ op = &stm_opcodes[opcode];
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+ reg = spiflash_wait_busy(priv);
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+ spiflash_write_reg(priv, SPI_FLASH_OPCODE,
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+ ((u32)op->code) | (addr << 8));
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+
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+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
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+ reg |= SPI_CTL_START | op->tx_cnt | (op->rx_cnt << 4);
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+
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+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
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+ spiflash_wait_busy(priv);
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+
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+ if (!op->rx_cnt)
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+ return 0;
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+
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+ reg = spiflash_read_reg(priv, SPI_FLASH_DATA);
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+
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+ switch (op->rx_cnt) {
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+ case 1:
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+ mask = 0x000000ff;
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+ break;
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+ case 2:
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+ mask = 0x0000ffff;
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+ break;
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+ case 3:
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+ mask = 0x00ffffff;
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+ break;
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+ default:
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+ mask = 0xffffffff;
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+ break;
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+ }
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+ reg &= mask;
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+
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+ return reg;
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+}
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+
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+/*
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+ * Probe SPI flash device
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+ * Function returns 0 for failure.
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+ * and flashconfig_tbl array index for success.
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+ */
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+static int
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+spiflash_probe_chip(struct platform_device *pdev, struct spiflash_priv *priv)
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+{
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+ u32 sig = spiflash_sendcmd(priv, SPI_RD_SIG, 0);
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+ int flash_size;
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+
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+ switch (sig) {
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+ case STM_8MBIT_SIGNATURE:
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+ flash_size = FLASH_1MB;
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+ break;
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+ case STM_16MBIT_SIGNATURE:
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+ flash_size = FLASH_2MB;
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+ break;
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+ case STM_32MBIT_SIGNATURE:
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+ flash_size = FLASH_4MB;
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+ break;
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+ case STM_64MBIT_SIGNATURE:
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+ flash_size = FLASH_8MB;
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+ break;
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+ case STM_128MBIT_SIGNATURE:
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+ flash_size = FLASH_16MB;
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+ break;
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+ default:
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+ dev_warn(&pdev->dev, "read of flash device signature failed!\n");
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+ return 0;
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+ }
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+
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+ return flash_size;
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+}
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+
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+static void
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+spiflash_wait_complete(struct spiflash_priv *priv, unsigned int timeout)
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+{
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+ busy_wait(priv, spiflash_sendcmd(priv, SPI_RD_STATUS, 0) &
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+ SPI_STATUS_WIP, timeout);
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+}
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+
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+static int
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+spiflash_erase(struct mtd_info *mtd, struct erase_info *instr)
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+{
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+ struct spiflash_priv *priv = to_spiflash(mtd);
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+ const struct opcodes *op;
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+ u32 temp, reg;
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+
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+ if (instr->addr + instr->len > mtd->size)
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+ return -EINVAL;
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+
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+ mutex_lock(&priv->lock);
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+
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+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
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+ reg = spiflash_wait_busy(priv);
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+
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+ op = &stm_opcodes[SPI_SECTOR_ERASE];
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+ temp = ((u32)instr->addr << 8) | (u32)(op->code);
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+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, temp);
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+
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+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
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+ reg |= op->tx_cnt | SPI_CTL_START;
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+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
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+
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+ spiflash_wait_complete(priv, 20);
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+
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+ mutex_unlock(&priv->lock);
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+
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+ instr->state = MTD_ERASE_DONE;
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+ mtd_erase_callback(instr);
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+
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+ return 0;
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+}
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+
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+static int
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+spiflash_read(struct mtd_info *mtd, loff_t from, size_t len, size_t *retlen,
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+ u_char *buf)
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+{
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+ struct spiflash_priv *priv = to_spiflash(mtd);
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+
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+ if (!len)
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+ return 0;
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+
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+ if (from + len > mtd->size)
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+ return -EINVAL;
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+
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+ *retlen = len;
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+
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+ mutex_lock(&priv->lock);
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+
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+ memcpy_fromio(buf, priv->readaddr + from, len);
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+
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+ mutex_unlock(&priv->lock);
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+
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+ return 0;
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+}
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+
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+static int
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+spiflash_write(struct mtd_info *mtd, loff_t to, size_t len, size_t *retlen,
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+ const u8 *buf)
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+{
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+ struct spiflash_priv *priv = to_spiflash(mtd);
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+ u32 opcode, bytes_left;
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+
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+ *retlen = 0;
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+
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+ if (!len)
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+ return 0;
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+
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+ if (to + len > mtd->size)
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+ return -EINVAL;
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+
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+ bytes_left = len;
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+
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+ do {
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+ u32 read_len, reg, page_offset, spi_data = 0;
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+
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+ read_len = min(bytes_left, sizeof(u32));
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+
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+ /* 32-bit writes cannot span across a page boundary
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+ * (256 bytes). This types of writes require two page
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+ * program operations to handle it correctly. The STM part
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+ * will write the overflow data to the beginning of the
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+ * current page as opposed to the subsequent page.
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+ */
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+ page_offset = (to & (STM_PAGE_SIZE - 1)) + read_len;
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+
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+ if (page_offset > STM_PAGE_SIZE)
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+ read_len -= (page_offset - STM_PAGE_SIZE);
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+
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+ mutex_lock(&priv->lock);
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+
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+ spiflash_sendcmd(priv, SPI_WRITE_ENABLE, 0);
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+ spi_data = 0;
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+ switch (read_len) {
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+ case 4:
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+ spi_data |= buf[3] << 24;
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+ /* fall through */
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+ case 3:
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+ spi_data |= buf[2] << 16;
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+ /* fall through */
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+ case 2:
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+ spi_data |= buf[1] << 8;
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+ /* fall through */
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+ case 1:
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+ spi_data |= buf[0] & 0xff;
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+ break;
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+ default:
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+ break;
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+ }
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+
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+ spiflash_write_reg(priv, SPI_FLASH_DATA, spi_data);
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+ opcode = stm_opcodes[SPI_PAGE_PROGRAM].code |
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+ (to & 0x00ffffff) << 8;
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+ spiflash_write_reg(priv, SPI_FLASH_OPCODE, opcode);
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+
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+ reg = spiflash_read_reg(priv, SPI_FLASH_CTL);
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+ reg &= ~SPI_CTL_TX_RX_CNT_MASK;
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+ reg |= (read_len + 4) | SPI_CTL_START;
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+ spiflash_write_reg(priv, SPI_FLASH_CTL, reg);
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+
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+ spiflash_wait_complete(priv, 1);
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+
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+ mutex_unlock(&priv->lock);
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+
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+ bytes_left -= read_len;
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+ to += read_len;
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+ buf += read_len;
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+
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+ *retlen += read_len;
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+ } while (bytes_left != 0);
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+
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+ return 0;
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+}
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+
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+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
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+static const char * const part_probe_types[] = {
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+ "cmdlinepart", "RedBoot", "MyLoader", NULL
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+};
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+#endif
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+
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+static int
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+spiflash_probe(struct platform_device *pdev)
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+{
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+ struct spiflash_priv *priv;
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+ struct mtd_info *mtd;
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+ struct resource *res;
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+ int index;
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+ int result = 0;
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+
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+ priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
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+ if (!priv)
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+ return -ENOMEM;
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+
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+ mutex_init(&priv->lock);
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+ mtd = &priv->mtd;
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
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+ priv->mmraddr = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(priv->mmraddr)) {
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+ dev_warn(&pdev->dev, "failed to map flash MMR\n");
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+ return PTR_ERR(priv->mmraddr);
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+ }
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+
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+ index = spiflash_probe_chip(pdev, priv);
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+ if (!index) {
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+ dev_warn(&pdev->dev, "found no flash device\n");
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+ return -ENODEV;
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+ }
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+
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+ res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
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+ priv->readaddr = devm_ioremap_resource(&pdev->dev, res);
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+ if (IS_ERR(priv->readaddr)) {
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+ dev_warn(&pdev->dev, "failed to map flash read mem\n");
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+ return PTR_ERR(priv->readaddr);
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+ }
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+
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+ platform_set_drvdata(pdev, priv);
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+ mtd->name = "spiflash";
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+ mtd->type = MTD_NORFLASH;
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+ mtd->flags = (MTD_CAP_NORFLASH|MTD_WRITEABLE);
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+ mtd->size = flashconfig_tbl[index].byte_cnt;
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+ mtd->erasesize = flashconfig_tbl[index].sector_size;
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+ mtd->writesize = 1;
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+ mtd->numeraseregions = 0;
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+ mtd->eraseregions = NULL;
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+ mtd->_erase = spiflash_erase;
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+ mtd->_read = spiflash_read;
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+ mtd->_write = spiflash_write;
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+ mtd->owner = THIS_MODULE;
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+
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+ dev_info(&pdev->dev, "%lld Kbytes flash detected\n", mtd->size >> 10);
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+
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+#if defined CONFIG_MTD_REDBOOT_PARTS || CONFIG_MTD_MYLOADER_PARTS
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+ /* parse redboot partitions */
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+
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+ result = mtd_device_parse_register(mtd, part_probe_types,
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+ NULL, NULL, 0);
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+#endif
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+
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+ return result;
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+}
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+
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+static int
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+spiflash_remove(struct platform_device *pdev)
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+{
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+ struct spiflash_priv *priv = platform_get_drvdata(pdev);
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+
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+ mtd_device_unregister(&priv->mtd);
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+
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+ return 0;
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+}
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+
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+static struct platform_driver spiflash_driver = {
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+ .driver.name = DRIVER_NAME,
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+ .probe = spiflash_probe,
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+ .remove = spiflash_remove,
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+};
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+
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+module_platform_driver(spiflash_driver);
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+
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+MODULE_LICENSE("GPL");
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|
+MODULE_AUTHOR("OpenWrt.org");
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|
+MODULE_AUTHOR("Atheros Communications Inc");
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|
+MODULE_DESCRIPTION("MTD driver for SPI Flash on Atheros AR2315+ SOC");
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|
+MODULE_ALIAS("platform:" DRIVER_NAME);
|
|
+
|
|
--- /dev/null
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|
+++ b/drivers/mtd/devices/ar2315_spiflash.h
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|
@@ -0,0 +1,106 @@
|
|
+/*
|
|
+ * Atheros AR2315 SPI Flash Memory support header file.
|
|
+ *
|
|
+ * Copyright (c) 2005, Atheros Communications Inc.
|
|
+ * Copyright (C) 2006 FON Technology, SL.
|
|
+ * Copyright (C) 2006 Imre Kaloz <kaloz@openwrt.org>
|
|
+ * Copyright (C) 2006-2009 Felix Fietkau <nbd@openwrt.org>
|
|
+ *
|
|
+ * This code is free software; you can redistribute it and/or modify
|
|
+ * it under the terms of the GNU General Public License version 2 as
|
|
+ * published by the Free Software Foundation.
|
|
+ *
|
|
+ */
|
|
+#ifndef __AR2315_SPIFLASH_H
|
|
+#define __AR2315_SPIFLASH_H
|
|
+
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+#define STM_PAGE_SIZE 256
|
|
+
|
|
+#define SFI_WRITE_BUFFER_SIZE 4
|
|
+#define SFI_FLASH_ADDR_MASK 0x00ffffff
|
|
+
|
|
+#define STM_8MBIT_SIGNATURE 0x13
|
|
+#define STM_M25P80_BYTE_COUNT 1048576
|
|
+#define STM_M25P80_SECTOR_COUNT 16
|
|
+#define STM_M25P80_SECTOR_SIZE 0x10000
|
|
+
|
|
+#define STM_16MBIT_SIGNATURE 0x14
|
|
+#define STM_M25P16_BYTE_COUNT 2097152
|
|
+#define STM_M25P16_SECTOR_COUNT 32
|
|
+#define STM_M25P16_SECTOR_SIZE 0x10000
|
|
+
|
|
+#define STM_32MBIT_SIGNATURE 0x15
|
|
+#define STM_M25P32_BYTE_COUNT 4194304
|
|
+#define STM_M25P32_SECTOR_COUNT 64
|
|
+#define STM_M25P32_SECTOR_SIZE 0x10000
|
|
+
|
|
+#define STM_64MBIT_SIGNATURE 0x16
|
|
+#define STM_M25P64_BYTE_COUNT 8388608
|
|
+#define STM_M25P64_SECTOR_COUNT 128
|
|
+#define STM_M25P64_SECTOR_SIZE 0x10000
|
|
+
|
|
+#define STM_128MBIT_SIGNATURE 0x17
|
|
+#define STM_M25P128_BYTE_COUNT 16777216
|
|
+#define STM_M25P128_SECTOR_COUNT 256
|
|
+#define STM_M25P128_SECTOR_SIZE 0x10000
|
|
+
|
|
+#define STM_1MB_BYTE_COUNT STM_M25P80_BYTE_COUNT
|
|
+#define STM_1MB_SECTOR_COUNT STM_M25P80_SECTOR_COUNT
|
|
+#define STM_1MB_SECTOR_SIZE STM_M25P80_SECTOR_SIZE
|
|
+#define STM_2MB_BYTE_COUNT STM_M25P16_BYTE_COUNT
|
|
+#define STM_2MB_SECTOR_COUNT STM_M25P16_SECTOR_COUNT
|
|
+#define STM_2MB_SECTOR_SIZE STM_M25P16_SECTOR_SIZE
|
|
+#define STM_4MB_BYTE_COUNT STM_M25P32_BYTE_COUNT
|
|
+#define STM_4MB_SECTOR_COUNT STM_M25P32_SECTOR_COUNT
|
|
+#define STM_4MB_SECTOR_SIZE STM_M25P32_SECTOR_SIZE
|
|
+#define STM_8MB_BYTE_COUNT STM_M25P64_BYTE_COUNT
|
|
+#define STM_8MB_SECTOR_COUNT STM_M25P64_SECTOR_COUNT
|
|
+#define STM_8MB_SECTOR_SIZE STM_M25P64_SECTOR_SIZE
|
|
+#define STM_16MB_BYTE_COUNT STM_M25P128_BYTE_COUNT
|
|
+#define STM_16MB_SECTOR_COUNT STM_M25P128_SECTOR_COUNT
|
|
+#define STM_16MB_SECTOR_SIZE STM_M25P128_SECTOR_SIZE
|
|
+
|
|
+/*
|
|
+ * ST Microelectronics Opcodes for Serial Flash
|
|
+ */
|
|
+
|
|
+#define STM_OP_WR_ENABLE 0x06 /* Write Enable */
|
|
+#define STM_OP_WR_DISABLE 0x04 /* Write Disable */
|
|
+#define STM_OP_RD_STATUS 0x05 /* Read Status */
|
|
+#define STM_OP_WR_STATUS 0x01 /* Write Status */
|
|
+#define STM_OP_RD_DATA 0x03 /* Read Data */
|
|
+#define STM_OP_FAST_RD_DATA 0x0b /* Fast Read Data */
|
|
+#define STM_OP_PAGE_PGRM 0x02 /* Page Program */
|
|
+#define STM_OP_SECTOR_ERASE 0xd8 /* Sector Erase */
|
|
+#define STM_OP_BULK_ERASE 0xc7 /* Bulk Erase */
|
|
+#define STM_OP_DEEP_PWRDOWN 0xb9 /* Deep Power-Down Mode */
|
|
+#define STM_OP_RD_SIG 0xab /* Read Electronic Signature */
|
|
+
|
|
+#define STM_STATUS_WIP 0x01 /* Write-In-Progress */
|
|
+#define STM_STATUS_WEL 0x02 /* Write Enable Latch */
|
|
+#define STM_STATUS_BP0 0x04 /* Block Protect 0 */
|
|
+#define STM_STATUS_BP1 0x08 /* Block Protect 1 */
|
|
+#define STM_STATUS_BP2 0x10 /* Block Protect 2 */
|
|
+#define STM_STATUS_SRWD 0x80 /* Status Register Write Disable */
|
|
+
|
|
+/*
|
|
+ * SPI Flash Interface Registers
|
|
+ */
|
|
+
|
|
+#define SPI_FLASH_CTL 0x00
|
|
+#define SPI_FLASH_OPCODE 0x04
|
|
+#define SPI_FLASH_DATA 0x08
|
|
+
|
|
+#define SPI_CTL_START 0x00000100
|
|
+#define SPI_CTL_BUSY 0x00010000
|
|
+#define SPI_CTL_TXCNT_MASK 0x0000000f
|
|
+#define SPI_CTL_RXCNT_MASK 0x000000f0
|
|
+#define SPI_CTL_TX_RX_CNT_MASK 0x000000ff
|
|
+#define SPI_CTL_SIZE_MASK 0x00060000
|
|
+
|
|
+#define SPI_CTL_CLK_SEL_MASK 0x03000000
|
|
+#define SPI_OPCODE_MASK 0x000000ff
|
|
+
|
|
+#define SPI_STATUS_WIP STM_STATUS_WIP
|
|
+
|
|
+#endif
|