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4ef86c620f
FCC ID: A8J-EPG600 Engenius EPG600 is an indoor wireless router with 1 Gb ethernet switch, dual-band wireless, internal antenna plates, USB, and phone lines (not supported) this board is a Senao device: the hardware is equivalent to EnGenius ESR600 (except for phone lines) the software is Senao SDK which is based on openwrt and uboot which uses the legacy Senao header with Vendor / Product IDs to verify the firmware upgrade image. **Specification:** - MT7620 SOC MIPS 24kec, 2.4 GHz WMAC, 2x2 - RT5592N WLAN PCI chip, 5 GHz, 2x2 - QCA8337N Gb SW RGMII GbE, SW P0 -- SOC P5, 5 LEDs - 40 MHz clock - 16 MB FLASH MX25L12845EMI-10G - 64 MB RAM NT5TU32M16 - UART console J2, populated - USB 2.0 port direct to SOC - 6 GPIO LEDs power, 2G, 5G, wps2g, wps5g, line - 3 buttons reset, wps, "reg" (registeration) - 4 antennas internal omni-directional plates NOT YET SUPPORTED: VoIP - Si3050-FT + Si3019-FT Voice DAA, SPI control, PCM data - Phone Ports "TEL", "LINE" RJ11, 4P2C (2 pins) **MAC addresses:** MAC address labeled as MAC ADDRESS MACs present in both wifi cal data and uboot environment eth0.1/phy1 ---- *:82 rf 0x4 phy0 ---- *:83 factory 0x4 eth0.2 MAC *:b8 "wanaddr" **Installation:** Method 1: Firmware upgrade page: (if you cannot access the APs webpage) factory reset with the reset button connect ethernet to a computer OEM webpage at 192.168.0.1 username and password 'admin' Navigate to gear icon, "Device Management", "Tools" select the factory.dlf image Upload and verify checksum Method 2: Serial to upload initramfs: Follow directions for TFTP recovery upload and boot initramfs and do a sysupgrade **TFTP recovery:** Requires UART serial console, reset button does nothing rename initramfs-kernel.bin to 'uImageEPG600' make available on TFTP server at 192.168.99.8 power board, interrupt boot with "4" execute `tftpboot` and `bootm` (with the load address) **Return to OEM:** Images from OEM are provided, but not compatible with openwrt sysupgrade. So it must be modified. Alternatively, back up all mtd partitions before flashing **Note on switch registers:** The necessary registers needed for the QCA8337 switch can be read from interrupted boot (tftpboot, bootm) by using the following lines in the switch driver ar8327.c in the function 'ar8327_hw_config_of' where 'qca,ar8327-initvals' is parsed from DTS before the new register values are written: pr_info("0x04 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD0_MODE)); pr_info("0x08 %08x\n", ar8xxx_read(priv, AR8327_REG_PAD5_MODE)); pr_info("0x0c %08x\n", ar8xxx_read(priv, AR8327_REG_PAD6_MODE)); pr_info("0x10 %08x\n", ar8xxx_read(priv, AR8327_REG_POWER_ON_STRAP)); Signed-off-by: Michael Pratt <mcpratt@pm.me>
229 lines
3.5 KiB
Plaintext
229 lines
3.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "mt7620a.dtsi"
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#include <dt-bindings/gpio/gpio.h>
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#include <dt-bindings/input/input.h>
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/ {
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compatible = "engenius,epg600", "ralink,mt7620a-soc";
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model = "EnGenius EPG600";
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aliases {
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led-boot = &led_power;
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led-failsafe = &led_power;
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led-running = &led_power;
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led-upgrade = &led_power;
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};
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chosen {
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bootargs = "console=ttyS0,115200";
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};
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keys {
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compatible = "gpio-keys";
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reset {
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linux,code = <KEY_RESTART>;
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gpios = <&gpio0 1 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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wps {
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linux,code = <KEY_WPS_BUTTON>;
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gpios = <&gpio0 2 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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reg {
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linux,code = <BTN_0>;
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gpios = <&gpio2 7 GPIO_ACTIVE_LOW>;
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debounce-interval = <60>;
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};
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};
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leds {
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compatible = "gpio-leds";
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led_power: power {
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label = "amber:power";
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gpios = <&gpio0 9 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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wlan2g {
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label = "blue:wlan2g";
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gpios = <&gpio3 0 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wlan5g {
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label = "blue:wlan5g";
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gpios = <&gpio0 7 GPIO_ACTIVE_LOW>;
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};
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wps2g {
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label = "blue:wps2g";
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gpios = <&gpio1 15 GPIO_ACTIVE_LOW>;
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};
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wps5g {
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label = "amber:wps5g";
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gpios = <&gpio2 6 GPIO_ACTIVE_LOW>;
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};
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line {
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label = "blue:line";
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gpios = <&gpio2 14 GPIO_ACTIVE_LOW>;
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};
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};
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};
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&gpio1 {
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status = "okay";
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};
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&gpio2 {
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status = "okay";
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};
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&gpio3 {
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status = "okay";
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};
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&spi0 {
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status = "okay";
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flash@0 {
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compatible = "jedec,spi-nor";
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reg = <0>;
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spi-max-frequency = <30000000>;
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partitions {
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compatible = "fixed-partitions";
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#address-cells = <1>;
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#size-cells = <1>;
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partition@0 {
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label = "u-boot";
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reg = <0x0 0x30000>;
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read-only;
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};
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partition@30000 {
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label = "u-boot-env";
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reg = <0x30000 0x10000>;
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};
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factory: partition@40000 {
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label = "factory";
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reg = <0x40000 0x10000>;
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read-only;
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};
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rf: partition@50000 {
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label = "rf";
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reg = <0x50000 0x10000>;
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read-only;
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};
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partition@60000 {
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label = "firmware";
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reg = <0x60000 0xf40000>;
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compatible = "denx,uimage";
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};
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partition@fa0000 {
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label = "backup";
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reg = <0xfa0000 0x10000>;
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read-only;
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};
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partition@fb0000 {
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label = "storage";
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reg = <0xfb0000 0x50000>;
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read-only;
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};
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};
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};
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};
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ðernet {
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pinctrl-names = "default";
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pinctrl-0 = <&mdio_pins &rgmii1_pins &rgmii2_pins>;
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nvmem-cells = <&macaddr_rf_4>;
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nvmem-cell-names = "mac-address";
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port@5 {
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status = "okay";
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phy-mode = "rgmii-txid";
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mediatek,fixed-link = <1000 1 1 1>;
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};
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mdio-bus {
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status = "okay";
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ethernet-phy@0 {
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reg = <0>;
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phy-mode = "rgmii";
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qca,ar8327-initvals = <
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0x04 0x07600000 /* PORT0 PAD MODE CTRL */
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0x08 0x01000000 /* PORT5 PAD MODE CTRL */
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0x0c 0x07600000 /* PORT6 PAD MODE CTRL */
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0x10 0x40000000 /* POWER-ON STRAPPING */
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0x7c 0x0000007e /* PORT0_STATUS */
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0x94 0x0000007e /* PORT6_STATUS */
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>;
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};
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};
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};
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&gsw {
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mediatek,ephy-disable;
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};
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&pcie {
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status = "okay";
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};
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&pcie0 {
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wifi@0,1,0 {
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compatible = "pci1814,3091";
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reg = <0x0 1 0 0 0>;
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ralink,mtd-eeprom = <&factory 0x0>;
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};
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};
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&wmac {
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ralink,mtd-eeprom = <&rf 0x0>;
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};
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&ehci {
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status = "okay";
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};
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&ohci {
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status = "okay";
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};
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&state_default {
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default {
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groups = "ephy", "wled", "spi refclk", "i2c", "uartf", "nd_sd";
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function = "gpio";
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};
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};
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&rf {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_rf_4: macaddr@4 {
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reg = <0x4 0x6>;
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};
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};
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