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0806f8fc80
Following changes are made to the Lantiq kernel patches:
0001-MIPS-lantiq-add-pcie-driver.patch
The pci header isn't included by the of_pci header any longer
0024-MIPS-lantiq-revert-DSA-switch-driver-PMU-clock-chang.patch
Due to the merge of grx390 and ar10 clocks, extend support to grx390
0025-NET-MIPS-lantiq-adds-xrx200-legacy.patch
The do_carrier arguments was dropped from phy_link_change. The
phylib has always sets the third parameter to true so the flag is
always changed anyway.
of_get_phy_mode() returns an error, or 0 on success, and pass a
pointer, of type phy_interface_t, where the phy mode should be
stored now. So far an error wasn't considered. Print at least an
error message if something unexpected happens.
The stuck queue is now passed to xrx200_tx_timeout (the timeout
handler) but not used so far.
0028-NET-lantiq-various-etop-fixes.patch
ioremap has provided non-cached semantics by default since the Linux
2.6 days and was removed with kernel version 5.6.
of_get_phy_mode() returns an error, or 0 on success, and pass a
pointer, of type phy_interface_t, where the phy mode should be
stored now. So far an error wasn't considered. Print at least an
error message if something unexpected happens.
0042-arch-mips-increase-io_space_limit.patch
Move IO space extension to laniq specific file
Signed-off-by: Mathias Kresin <dev@kresin.me>
31 lines
720 B
Diff
31 lines
720 B
Diff
--- a/arch/mips/lantiq/xway/sysctrl.c
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+++ b/arch/mips/lantiq/xway/sysctrl.c
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@@ -426,6 +426,20 @@ static void clkdev_add_clkout(void)
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}
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}
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+static void set_phy_clock_source(struct device_node *np_cgu)
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+{
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+ u32 phy_clk_src, ifcc;
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+
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+ if (!np_cgu)
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+ return;
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+
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+ if (of_property_read_u32(np_cgu, "lantiq,phy-clk-src", &phy_clk_src))
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+ return;
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+
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+ ifcc = ltq_cgu_r32(ifccr) & ~(0x1c);
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+ ltq_cgu_w32(ifcc | (phy_clk_src << 2), ifccr);
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+}
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+
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/* bring up all register ranges that we need for basic system control */
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void __init ltq_soc_init(void)
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{
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@@ -591,4 +605,6 @@ void __init ltq_soc_init(void)
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clkdev_add_pmu("1e100400.serial", NULL, 1, 0, PMU_ASC0);
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}
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usb_set_clock();
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+
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+ set_phy_clock_source(np_cgu);
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}
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