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5d921aa72f
Add support for hardware I2C and PWM units found in the Filogic SoCs as well as the CPU thermal support. Signed-off-by: Daniel Golle <daniel@makrotopia.org>
150 lines
4.8 KiB
Diff
150 lines
4.8 KiB
Diff
From 1d5819e90f2ef6dead11809744372a9863227a92 Mon Sep 17 00:00:00 2001
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From: Zhanyong Wang <zhanyong.wang@mediatek.com>
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Date: Tue, 25 Jan 2022 19:03:34 +0800
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Subject: [PATCH 5/5] phy: phy-mtk-tphy: add auto-load-valid check mechanism
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support
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add auto-load-valid check mechanism support
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Signed-off-by: Zhanyong Wang <zhanyong.wang@mediatek.com>
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---
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drivers/phy/mediatek/phy-mtk-tphy.c | 67 +++++++++++++++++++++++++++--
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1 file changed, 64 insertions(+), 3 deletions(-)
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--- a/drivers/phy/mediatek/phy-mtk-tphy.c
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+++ b/drivers/phy/mediatek/phy-mtk-tphy.c
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@@ -376,9 +376,13 @@ struct mtk_phy_instance {
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u32 type_sw_reg;
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u32 type_sw_index;
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u32 efuse_sw_en;
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+ bool efuse_alv_en;
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+ u32 efuse_autoloadvalid;
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u32 efuse_intr;
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u32 efuse_tx_imp;
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u32 efuse_rx_imp;
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+ bool efuse_alv_ln1_en;
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+ u32 efuse_ln1_autoloadvalid;
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u32 efuse_intr_ln1;
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u32 efuse_tx_imp_ln1;
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u32 efuse_rx_imp_ln1;
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@@ -1125,6 +1129,7 @@ static int phy_efuse_get(struct mtk_tphy
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{
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struct device *dev = &instance->phy->dev;
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int ret = 0;
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+ bool alv = false;
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/* tphy v1 doesn't support sw efuse, skip it */
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if (!tphy->pdata->sw_efuse_supported) {
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@@ -1139,6 +1144,20 @@ static int phy_efuse_get(struct mtk_tphy
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switch (instance->type) {
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case PHY_TYPE_USB2:
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
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+ if (alv) {
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+ instance->efuse_alv_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
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+ &instance->efuse_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get u2 alv efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "u2 auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u2 intr efuse, %d\n", ret);
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@@ -1157,6 +1176,20 @@ static int phy_efuse_get(struct mtk_tphy
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case PHY_TYPE_USB3:
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case PHY_TYPE_PCIE:
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid");
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+ if (alv) {
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+ instance->efuse_alv_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid",
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+ &instance->efuse_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get u3(pcei) alv efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "u3 auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr", &instance->efuse_intr);
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if (ret) {
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dev_err(dev, "fail to get u3 intr efuse, %d\n", ret);
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@@ -1190,6 +1223,20 @@ static int phy_efuse_get(struct mtk_tphy
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if (tphy->pdata->version != MTK_PHY_V4)
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break;
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+ alv = of_property_read_bool(dev->of_node, "auto_load_valid_ln1");
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+ if (alv) {
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+ instance->efuse_alv_ln1_en = alv;
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+ ret = nvmem_cell_read_variable_le_u32(dev, "auto_load_valid_ln1",
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+ &instance->efuse_ln1_autoloadvalid);
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+ if (ret) {
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+ dev_err(dev, "fail to get pcie auto_load_valid efuse, %d\n", ret);
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+ break;
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+ }
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+ dev_info(dev,
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+ "pcie auto load valid efuse: ENABLE with value: %u\n",
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+ instance->efuse_ln1_autoloadvalid);
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+ }
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+
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ret = nvmem_cell_read_variable_le_u32(dev, "intr_ln1", &instance->efuse_intr_ln1);
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if (ret) {
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dev_err(dev, "fail to get u3 lane1 intr efuse, %d\n", ret);
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@@ -1241,6 +1288,10 @@ static void phy_efuse_set(struct mtk_phy
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switch (instance->type) {
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case PHY_TYPE_USB2:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u2_banks->misc + U3P_MISC_REG1);
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tmp |= MR1_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u2_banks->misc + U3P_MISC_REG1);
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@@ -1251,6 +1302,10 @@ static void phy_efuse_set(struct mtk_phy
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writel(tmp, u2_banks->com + U3P_USBPHYACR1);
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break;
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case PHY_TYPE_USB3:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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@@ -1277,6 +1332,10 @@ static void phy_efuse_set(struct mtk_phy
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break;
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case PHY_TYPE_PCIE:
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+ if (instance->efuse_alv_en &&
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+ instance->efuse_autoloadvalid == 1)
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+ break;
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+
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tmp = readl(u3_banks->phyd + U3P_U3_PHYD_RSV);
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tmp |= P3D_RG_EFUSE_AUTO_LOAD_DIS;
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writel(tmp, u3_banks->phyd + U3P_U3_PHYD_RSV);
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@@ -1297,9 +1356,12 @@ static void phy_efuse_set(struct mtk_phy
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tmp &= ~P3A_RG_IEXT_INTR;
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tmp |= P3A_RG_IEXT_INTR_VAL(instance->efuse_intr);
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writel(tmp, u3_banks->phya + U3P_U3_PHYA_REG0);
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- if (!instance->efuse_intr_ln1 &&
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- !instance->efuse_rx_imp_ln1 &&
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- !instance->efuse_tx_imp_ln1)
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+
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+ if ((!instance->efuse_intr_ln1 &&
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+ !instance->efuse_rx_imp_ln1 &&
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+ !instance->efuse_tx_imp_ln1) ||
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+ (instance->efuse_alv_ln1_en &&
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+ instance->efuse_ln1_autoloadvalid == 1))
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break;
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tmp = readl(u3_banks->phyd + SSUSB_LN1_OFFSET + U3P_U3_PHYD_RSV);
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