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https://github.com/openwrt/openwrt.git
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62b7f5931c
bcm2708: boot tested on RPi B+ v1.2
bcm2709: boot tested on RPi 3B v1.2 and RPi 4B v1.1 4G
bcm2710: boot tested on RPi 3B v1.2
bcm2711: boot tested on RPi 4B v1.1 4G
Signed-off-by: Álvaro Fernández Rojas <noltari@gmail.com>
(cherry-picked from commit f07e572f64
)
309 lines
10 KiB
Diff
309 lines
10 KiB
Diff
From 0eb6753788616ffed17a0484a14fd7d3df2a2a05 Mon Sep 17 00:00:00 2001
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From: Naushir Patuck <naush@raspberrypi.com>
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Date: Thu, 2 Apr 2020 16:08:51 +0100
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Subject: [PATCH] media: bcm2835-unicam: Use dummy buffer if none have
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been queued
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If no buffer has been queued by a userland application, we use an
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internal dummy buffer for the hardware to spin in. This will allow
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the driver to release the existing userland buffer back to the
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application for processing.
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Signed-off-by: Naushir Patuck <naush@raspberrypi.com>
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---
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.../media/platform/bcm2835/bcm2835-unicam.c | 160 ++++++++++++------
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1 file changed, 110 insertions(+), 50 deletions(-)
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--- a/drivers/media/platform/bcm2835/bcm2835-unicam.c
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+++ b/drivers/media/platform/bcm2835/bcm2835-unicam.c
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@@ -47,6 +47,7 @@
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#include <linux/clk.h>
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#include <linux/delay.h>
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#include <linux/device.h>
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+#include <linux/dma-mapping.h>
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#include <linux/err.h>
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#include <linux/init.h>
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#include <linux/interrupt.h>
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@@ -112,6 +113,12 @@ MODULE_PARM_DESC(debug, "Debug level 0-3
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/* Default size of the embedded buffer */
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#define UNICAM_EMBEDDED_SIZE 8192
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+/*
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+ * Size of the dummy buffer. Can be any size really, but the DMA
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+ * allocation works in units of page sizes.
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+ */
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+#define DUMMY_BUF_SIZE (PAGE_SIZE)
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+
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enum pad_types {
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IMAGE_PAD,
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METADATA_PAD,
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@@ -390,6 +397,12 @@ struct unicam_node {
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struct media_pad pad;
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struct v4l2_ctrl_handler ctrl_handler;
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unsigned int embedded_lines;
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+ /*
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+ * Dummy buffer intended to be used by unicam
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+ * if we have no other queued buffers to swap to.
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+ */
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+ void *dummy_buf_cpu_addr;
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+ dma_addr_t dummy_buf_dma_addr;
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};
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struct unicam_device {
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@@ -661,27 +674,24 @@ static int unicam_reset_format(struct un
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return 0;
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}
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-static void unicam_wr_dma_addr(struct unicam_device *dev, dma_addr_t dmaaddr,
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- int pad_id)
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+static void unicam_wr_dma_addr(struct unicam_cfg *cfg, dma_addr_t dmaaddr,
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+ unsigned int buffer_size, int pad_id)
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{
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- dma_addr_t endaddr;
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+ dma_addr_t endaddr = dmaaddr + buffer_size;
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/*
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- * dmaaddr should be a 32-bit address with the top two bits set to 0x3
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- * to signify uncached access through the Videocore memory controller.
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+ * dmaaddr and endaddr should be a 32-bit address with the top two bits
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+ * set to 0x3 to signify uncached access through the Videocore memory
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+ * controller.
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*/
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- BUG_ON((dmaaddr >> 30) != 0x3);
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+ BUG_ON((dmaaddr >> 30) != 0x3 && (endaddr >> 30) != 0x3);
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if (pad_id == IMAGE_PAD) {
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- endaddr = dmaaddr +
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- dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;
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- reg_write(&dev->cfg, UNICAM_IBSA0, dmaaddr);
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- reg_write(&dev->cfg, UNICAM_IBEA0, endaddr);
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+ reg_write(cfg, UNICAM_IBSA0, dmaaddr);
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+ reg_write(cfg, UNICAM_IBEA0, endaddr);
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} else {
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- endaddr = dmaaddr +
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- dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;
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- reg_write(&dev->cfg, UNICAM_DBSA0, dmaaddr);
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- reg_write(&dev->cfg, UNICAM_DBEA0, endaddr);
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+ reg_write(cfg, UNICAM_DBSA0, dmaaddr);
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+ reg_write(cfg, UNICAM_DBEA0, endaddr);
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}
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}
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@@ -704,6 +714,7 @@ static inline void unicam_schedule_next_
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struct unicam_device *dev = node->dev;
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struct unicam_dmaqueue *dma_q = &node->dma_queue;
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struct unicam_buffer *buf;
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+ unsigned int size;
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dma_addr_t addr;
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buf = list_entry(dma_q->active.next, struct unicam_buffer, list);
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@@ -711,7 +722,23 @@ static inline void unicam_schedule_next_
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list_del(&buf->list);
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addr = vb2_dma_contig_plane_dma_addr(&buf->vb.vb2_buf, 0);
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- unicam_wr_dma_addr(dev, addr, node->pad_id);
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+ size = (node->pad_id == IMAGE_PAD) ?
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+ dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage :
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+ dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;
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+
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+ unicam_wr_dma_addr(&dev->cfg, addr, size, node->pad_id);
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+}
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+
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+static inline void unicam_schedule_dummy_buffer(struct unicam_node *node)
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+{
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+ struct unicam_device *dev = node->dev;
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+ dma_addr_t addr = node->dummy_buf_dma_addr;
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+
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+ unicam_dbg(3, dev, "Scheduling dummy buffer for node %d\n",
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+ node->pad_id);
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+
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+ unicam_wr_dma_addr(&dev->cfg, addr, DUMMY_BUF_SIZE, node->pad_id);
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+ node->next_frm = NULL;
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}
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static inline void unicam_process_buffer_complete(struct unicam_node *node,
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@@ -721,7 +748,6 @@ static inline void unicam_process_buffer
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node->cur_frm->vb.sequence = sequence;
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vb2_buffer_done(&node->cur_frm->vb.vb2_buf, VB2_BUF_STATE_DONE);
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- node->cur_frm = node->next_frm;
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}
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static int unicam_num_nodes_streaming(struct unicam_device *dev)
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@@ -788,6 +814,28 @@ static irqreturn_t unicam_isr(int irq, v
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if (!(sta && (UNICAM_IS | UNICAM_PI0)))
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return IRQ_HANDLED;
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+ /*
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+ * We must run the frame end handler first. If we have a valid next_frm
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+ * and we get a simultaneout FE + FS interrupt, running the FS handler
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+ * first would null out the next_frm ptr and we would have lost the
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+ * buffer forever.
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+ */
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+ if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
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+ /*
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+ * Ensure we have swapped buffers already as we can't
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+ * stop the peripheral. If no buffer is available, use a
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+ * dummy buffer to dump out frames until we get a new buffer
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+ * to use.
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+ */
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+ for (i = 0; i < num_nodes_streaming; i++) {
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+ if (unicam->node[i].cur_frm)
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+ unicam_process_buffer_complete(&unicam->node[i],
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+ sequence);
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+ unicam->node[i].cur_frm = unicam->node[i].next_frm;
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+ }
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+ unicam->sequence++;
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+ }
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+
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if (ista & UNICAM_FSI) {
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/*
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* Timestamp is to be when the first data byte was captured,
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@@ -798,24 +846,16 @@ static irqreturn_t unicam_isr(int irq, v
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if (unicam->node[i].cur_frm)
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unicam->node[i].cur_frm->vb.vb2_buf.timestamp =
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ts;
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+ /*
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+ * Set the next frame output to go to a dummy frame
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+ * if we have not managed to obtain another frame
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+ * from the queue.
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+ */
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+ unicam_schedule_dummy_buffer(&unicam->node[i]);
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}
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}
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- if (ista & UNICAM_FEI || sta & UNICAM_PI0) {
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- /*
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- * Ensure we have swapped buffers already as we can't
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- * stop the peripheral. Overwrite the frame we've just
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- * captured instead.
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- */
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- for (i = 0; i < num_nodes_streaming; i++) {
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- if (unicam->node[i].cur_frm &&
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- unicam->node[i].cur_frm != unicam->node[i].next_frm)
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- unicam_process_buffer_complete(&unicam->node[i],
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- sequence);
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- }
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- unicam->sequence++;
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- }
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-
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- /* Cannot swap buffer at frame end, there may be a race condition
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+ /*
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+ * Cannot swap buffer at frame end, there may be a race condition
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* where the HW does not actually swap it if the new frame has
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* already started.
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*/
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@@ -823,7 +863,7 @@ static irqreturn_t unicam_isr(int irq, v
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for (i = 0; i < num_nodes_streaming; i++) {
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spin_lock(&unicam->node[i].dma_queue_lock);
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if (!list_empty(&unicam->node[i].dma_queue.active) &&
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- unicam->node[i].cur_frm == unicam->node[i].next_frm)
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+ !unicam->node[i].next_frm)
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unicam_schedule_next_buffer(&unicam->node[i]);
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spin_unlock(&unicam->node[i].dma_queue_lock);
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}
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@@ -1352,7 +1392,7 @@ static void unicam_start_rx(struct unica
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{
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struct unicam_cfg *cfg = &dev->cfg;
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int line_int_freq = dev->node[IMAGE_PAD].v_fmt.fmt.pix.height >> 2;
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- unsigned int i;
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+ unsigned int size, i;
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u32 val;
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if (line_int_freq < 128)
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@@ -1413,7 +1453,7 @@ static void unicam_start_rx(struct unica
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reg_write_field(cfg, UNICAM_ANA, 0, UNICAM_DDL);
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/* Always start in trigger frame capture mode (UNICAM_FCM set) */
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- val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM;
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+ val = UNICAM_FSIE | UNICAM_FEIE | UNICAM_FCM | UNICAM_IBOB;
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set_field(&val, line_int_freq, UNICAM_LCIE_MASK);
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reg_write(cfg, UNICAM_ICTL, val);
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reg_write(cfg, UNICAM_STA, UNICAM_STA_MASK_ALL);
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@@ -1501,7 +1541,8 @@ static void unicam_start_rx(struct unica
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reg_write(&dev->cfg, UNICAM_IBLS,
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dev->node[IMAGE_PAD].v_fmt.fmt.pix.bytesperline);
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- unicam_wr_dma_addr(dev, addr[IMAGE_PAD], IMAGE_PAD);
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+ size = dev->node[IMAGE_PAD].v_fmt.fmt.pix.sizeimage;
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+ unicam_wr_dma_addr(&dev->cfg, addr[IMAGE_PAD], size, IMAGE_PAD);
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unicam_set_packing_config(dev);
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unicam_cfg_image_id(dev);
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@@ -1511,8 +1552,10 @@ static void unicam_start_rx(struct unica
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reg_write(cfg, UNICAM_MISC, val);
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if (dev->node[METADATA_PAD].streaming && dev->sensor_embedded_data) {
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+ size = dev->node[METADATA_PAD].v_fmt.fmt.meta.buffersize;
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unicam_enable_ed(dev);
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- unicam_wr_dma_addr(dev, addr[METADATA_PAD], METADATA_PAD);
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+ unicam_wr_dma_addr(&dev->cfg, addr[METADATA_PAD], size,
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+ METADATA_PAD);
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}
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/* Enable peripheral */
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@@ -1686,13 +1729,14 @@ static void unicam_stop_streaming(struct
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unicam_runtime_put(dev);
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} else if (node->pad_id == METADATA_PAD) {
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- /* Null out the embedded data buffer address so the HW does
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- * not use it. This is only really needed if the embedded data
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- * pad is disabled before the image pad. The 0x3 in the top two
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- * bits signifies uncached accesses through the Videocore
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- * memory controller.
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+ /* Allow the hardware to spin in the dummy buffer.
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+ * This is only really needed if the embedded data pad is
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+ * disabled before the image pad. The 0x3 in the top two bits
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+ * signifies uncached accesses through the Videocore memory
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+ * controller.
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*/
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- unicam_wr_dma_addr(dev, 0xc0000000, METADATA_PAD);
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+ unicam_wr_dma_addr(&dev->cfg, node->dummy_buf_dma_addr,
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+ DUMMY_BUF_SIZE, METADATA_PAD);
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}
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/* Clear all queued buffers for the node */
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@@ -2321,6 +2365,15 @@ static int register_node(struct unicam_d
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video_set_drvdata(vdev, node);
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vdev->entity.flags |= MEDIA_ENT_FL_DEFAULT;
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+ node->dummy_buf_cpu_addr = dma_alloc_coherent(&unicam->pdev->dev,
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+ DUMMY_BUF_SIZE,
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+ &node->dummy_buf_dma_addr,
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+ GFP_ATOMIC);
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+ if (!node->dummy_buf_cpu_addr) {
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+ unicam_err(unicam, "Unable to allocate dummy buffer.\n");
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+ return -ENOMEM;
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+ }
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+
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if (node->pad_id == METADATA_PAD ||
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!v4l2_subdev_has_op(unicam->sensor, video, s_std)) {
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v4l2_disable_ioctl(&node->video_dev, VIDIOC_S_STD);
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@@ -2376,13 +2429,20 @@ static int register_node(struct unicam_d
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static void unregister_nodes(struct unicam_device *unicam)
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{
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- if (unicam->node[IMAGE_PAD].registered) {
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- video_unregister_device(&unicam->node[IMAGE_PAD].video_dev);
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- unicam->node[IMAGE_PAD].registered = 0;
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- }
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- if (unicam->node[METADATA_PAD].registered) {
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- video_unregister_device(&unicam->node[METADATA_PAD].video_dev);
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- unicam->node[METADATA_PAD].registered = 0;
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+ struct unicam_node *node;
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+ int i;
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+
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+ for (i = 0; i < MAX_NODES; i++) {
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+ node = &unicam->node[i];
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+ if (node->dummy_buf_cpu_addr) {
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+ dma_free_coherent(&unicam->pdev->dev, DUMMY_BUF_SIZE,
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+ node->dummy_buf_cpu_addr,
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+ node->dummy_buf_dma_addr);
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+ }
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+ if (node->registered) {
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+ video_unregister_device(&node->video_dev);
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+ node->registered = 0;
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+ }
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}
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}
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