mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 18:19:02 +00:00
9b90dc05f5
This patch is based on #1689 and adds support for TP-Link Archer C6 v2 (US) and A6 (US/TW). The hardware is the same as EU and RU variant, except for GPIOs (LEDS/Buttons), flash(chip/partitions) and UART being available on the board. - SOC: Qualcomm QCA9563 @ 775MHz - Flash: GigaDevice GD25Q127CS1G (16MiB) - RAM: Zentel A3R1GE40JBF (128 MiB DDR2) - Ethernet: Qualcomm QCA8337N: 4x 1Gbps LAN + 1x 1Gbps WAN - Wireless: - 2.4GHz (bgn) QCA9563 integrated (3x3) - 5GHz (ac) Qualcomm QCA9886 (2x2) - Button: 1x power, 1x reset, 1x wps - LED: 6x LEDs: power, wlan2g, wlan5g, lan, wan, wps - UART: 115200, 8n1 (header available on board) Known issues: - Wireless: 5GHz is known to have lower RSSI signal, it affects speed and range. Flash instructions: Upload openwrt-ath79-generic-tplink_archer-c6-v2-us-squashfs-factory.bin via the router Web interface. Flash instruction using tftp recovery: 1. Connect the computer to one of the LAN ports of the router 2. Set the computer IP to 192.168.0.66 3. Start a tftp server with the OpenWrt factory image in the tftp root directory renamed to ArcherA6v2_tp_recovery.bin. 4. Connect power cable to router, press and hold the reset button and turn the router on 5. Keep the reset button pressed until the WPS LED lights up 6. Wait ~150 seconds to complete flashing Flash partitioning: I've followed #1689 for defining the partition layout for this patch. The partition named as "tplink" @ 0xfd0000 is marked as read only as it is where some config for stock firmware are stored. On stock firmware those stock partitions starts at 0xfd9400 however I had not been able to make it functional starting on the same address as on stock fw, so it has been partitioned following #1689 and not the stock partition layout for this specific partition. Due to that firmware/rootfs partition lenght is 0xf80000 and not 0xf89400 as stock. According to the GPL code, the EU/RU/JP variant does have different GPIO pins assignment to LEDs and buttons, also the flash memory layout is different. GPL Source Code: https://static.tp-link.com/resources/gpl/gpl-A6v2_us.tar.gz Signed-off-by: Anderson Vulczak <andi@andi.com.br> [wrap commit message, remove soft_ver change for C6 v2 EU, move LED aliases to DTS files, remove dts-v1 in DTSI, node/property reorder in DTSI] Signed-off-by: Adrian Schmutzler <freifunk@adrianschmutzler.de>
125 lines
2.1 KiB
Plaintext
125 lines
2.1 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
|
|
/dts-v1/;
|
|
|
|
#include "qca9563_tplink_archer-x6-v2.dtsi"
|
|
|
|
/ {
|
|
compatible = "tplink,archer-c6-v2", "qca,qca9563";
|
|
model = "TP-Link Archer C6 v2 (EU/RU/JP)";
|
|
|
|
aliases {
|
|
led-boot = &led_power;
|
|
led-failsafe = &led_power;
|
|
led-running = &led_power;
|
|
led-upgrade = &led_power;
|
|
};
|
|
|
|
leds {
|
|
compatible = "gpio-leds";
|
|
|
|
led_power: power {
|
|
label = "tp-link:green:power";
|
|
gpios = <&gpio 17 GPIO_ACTIVE_LOW>;
|
|
default-state = "on";
|
|
};
|
|
|
|
wlan2g {
|
|
label = "tp-link:green:wlan2g";
|
|
gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy1tpt";
|
|
};
|
|
|
|
wlan5g {
|
|
label = "tp-link:green:wlan5g";
|
|
gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
|
|
linux,default-trigger = "phy0tpt";
|
|
};
|
|
|
|
lan {
|
|
label = "tp-link:green:lan";
|
|
gpios = <&gpio 20 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wan {
|
|
label = "tp-link:green:wan";
|
|
gpios = <&gpio 7 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wan_fail {
|
|
label = "tp-link:amber:wan";
|
|
gpios = <&gpio 8 GPIO_ACTIVE_LOW>;
|
|
};
|
|
|
|
wps {
|
|
label = "tp-link:green:wps";
|
|
gpios = <&gpio 9 GPIO_ACTIVE_LOW>;
|
|
};
|
|
};
|
|
|
|
keys {
|
|
compatible = "gpio-keys";
|
|
|
|
reset {
|
|
label = "Reset button";
|
|
linux,code = <KEY_RESTART>;
|
|
gpios = <&gpio 5 GPIO_ACTIVE_LOW>;
|
|
debounce-interval = <60>;
|
|
};
|
|
|
|
wps {
|
|
label = "WPS button";
|
|
linux,code = <KEY_WPS_BUTTON>;
|
|
gpios = <&gpio 6 GPIO_ACTIVE_LOW>;
|
|
debounce-interval = <60>;
|
|
};
|
|
};
|
|
};
|
|
|
|
&spi {
|
|
status = "okay";
|
|
|
|
num-cs = <1>;
|
|
|
|
flash@0 {
|
|
compatible = "jedec,spi-nor";
|
|
reg = <0>;
|
|
spi-max-frequency = <25000000>;
|
|
|
|
partitions {
|
|
compatible = "fixed-partitions";
|
|
#address-cells = <1>;
|
|
#size-cells = <1>;
|
|
|
|
partition@0 {
|
|
label = "u-boot";
|
|
reg = <0x000000 0x020000>;
|
|
read-only;
|
|
};
|
|
|
|
mac: partition@20000 {
|
|
label = "mac";
|
|
reg = <0x020000 0x010000>;
|
|
read-only;
|
|
};
|
|
|
|
partition@30000 {
|
|
compatible = "denx,uimage";
|
|
label = "firmware";
|
|
reg = <0x030000 0x7a0000>;
|
|
};
|
|
|
|
partition@7d0000 {
|
|
label = "tplink";
|
|
reg = <0x7d0000 0x020000>;
|
|
read-only;
|
|
};
|
|
|
|
art: partition@7f0000 {
|
|
label = "art";
|
|
reg = <0x7f0000 0x010000>;
|
|
read-only;
|
|
};
|
|
};
|
|
};
|
|
};
|