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8b3d879861
Refreshed all patches. Compile-tested on: ath79, lantiq, ipq40xx, x86_64 Runtime-tested on: ipq40xx, x86_64 Signed-off-by: Hauke Mehrtens <hauke@hauke-m.de>
30 lines
1.3 KiB
Diff
30 lines
1.3 KiB
Diff
From 707745e8d4e75b638b990d67950ab292b3b8ea2a Mon Sep 17 00:00:00 2001
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From: David Bauer <mail@david-bauer.net>
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Date: Mon, 16 Dec 2019 01:36:46 +0100
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Subject: [PATCH] mtd: spi-nor: Add support for mx25r3235f
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Add MTD support for the Macronix MX25R3235F SPI NOR chip from Macronix.
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The chip has 4MB of total capacity, divided into a total of 64 sectors,
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each 64KB sized. The chip also supports 4KB large sectors.
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Additionally, it supports dual and quad read modes.
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Functionality was verified on an HPE/Aruba AP-303 board.
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Signed-off-by: David Bauer <mail@david-bauer.net>
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Signed-off-by: Tudor Ambarus <tudor.ambarus@microchip.com>
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---
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drivers/mtd/spi-nor/spi-nor.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/mtd/spi-nor/spi-nor.c
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+++ b/drivers/mtd/spi-nor/spi-nor.c
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@@ -2353,6 +2353,8 @@ static const struct flash_info spi_nor_i
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{ "mx25u6435f", INFO(0xc22537, 0, 64 * 1024, 128, SECT_4K) },
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{ "mx25l12805d", INFO(0xc22018, 0, 64 * 1024, 256, 0) },
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{ "mx25l12855e", INFO(0xc22618, 0, 64 * 1024, 256, 0) },
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+ { "mx25r3235f", INFO(0xc22816, 0, 64 * 1024, 64,
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+ SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "mx25u12835f", INFO(0xc22538, 0, 64 * 1024, 256,
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SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) },
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{ "mx25l25635e", INFO(0xc22019, 0, 64 * 1024, 512,
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