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5df1b33298
FCC ID: U2M-CAP2100AG
WatchGuard AP100 is an indoor wireless access point with
1 Gb ethernet port, dual-band but single-radio wireless,
internal antenna plates, and 802.3at PoE+
this board is a Senao device:
the hardware is equivalent to EnGenius EAP300 v2
the software is modified Senao SDK which is based on openwrt and uboot
including image checksum verification at boot time,
and a failsafe image that boots if checksum fails
**Specification:**
- AR9344 SOC MIPS 74kc, 2.4 GHz AND 5 GHz WMAC, 2x2
- AR8035-A EPHY RGMII GbE with PoE+ IN
- 25 MHz clock
- 16 MB FLASH mx25l12805d
- 2x 64 MB RAM
- UART console J11, populated
- GPIO watchdog GPIO 16, 20 sec toggle
- 2 antennas 5 dBi, internal omni-directional plates
- 5 LEDs power, eth0 link/data, 2G, 5G
- 1 button reset
**MAC addresses:**
Label has no MAC
Only one Vendor MAC address in flash at art 0x0
eth0 ---- *:e5 art 0x0 -2
phy0 ---- *:e5 art 0x0 -2
**Installation:**
Method 1: OEM webpage
use OEM webpage for firmware upgrade to upload factory.bin
Method 2: root shell
It may be necessary to use a Watchguard router to flash the image to the AP
and / or to downgrade the software on the AP to access SSH
For some Watchguard devices, serial console over UART is disabled.
NOTE: DHCP is not enabled by default after flashing
**TFTP recovery:**
reset button has no function at boot time
only possible with modified uboot environment,
(see commit message for Watchguard AP300)
**Return to OEM:**
user should make backup of MTD partitions
and write the backups back to mtd devices
in order to revert to OEM reliably
It may be possible to use sysupgrade
with an OEM image as well...
(not tested)
**OEM upgrade info:**
The OEM upgrade script is at /etc/fwupgrade.sh
OKLI kernel loader is required because the OEM software
expects the kernel to be no greater than 1536k
and the factory.bin upgrade procedure would otherwise
overwrite part of the kernel when writing rootfs.
**Note on eth0 PLL-data:**
The default Ethernet Configuration register values will not work
because of the external AR8035 switch between
the SOC and the ethernet port.
For AR934x series, the PLL registers for eth0
can be see in the DTSI as 0x2c.
Therefore the PLL registers can be read from uboot
for each link speed after attempting tftpboot
or another network action using that link speed
with `md 0x1805002c 1`.
The clock delay required for RGMII can be applied
at the PHY side, using the at803x driver `phy-mode`.
Therefore the PLL registers for GMAC0
do not need the bits for delay on the MAC side.
This is possible due to fixes in at803x driver
since Linux 5.1 and 5.3
**Note on WatchGuard Magic string:**
The OEM upgrade script is a modified version of
the generic Senao sysupgrade script
which is used on EnGenius devices.
On WatchGuard boards produced by Senao,
images are verified using a md5sum checksum of
the upgrade image concatenated with a magic string.
this checksum is then appended to the end of the final image.
This variable does not apply to all the senao devices
so set to null string as default
Tested-by: Steve Wheeler <stephenw10@gmail.com>
Signed-off-by: Michael Pratt <mcpratt@pm.me>
85 lines
1.5 KiB
Plaintext
85 lines
1.5 KiB
Plaintext
// SPDX-License-Identifier: GPL-2.0-or-later OR MIT
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#include "ar9344_senao_ap-dual.dtsi"
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/ {
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compatible = "watchguard,ap100", "qca,ar9344";
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model = "WatchGuard AP100";
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aliases {
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led-boot = &led_power_amber;
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led-failsafe = &led_power_amber;
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led-running = &led_power_green;
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led-upgrade = &led_power_amber;
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};
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leds {
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compatible = "gpio-leds";
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led_power_amber: power_amber {
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label = "amber:power";
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gpios = <&gpio 13 GPIO_ACTIVE_LOW>;
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};
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led_power_green: power_green {
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label = "green:power";
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gpios = <&gpio 12 GPIO_ACTIVE_LOW>;
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default-state = "on";
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};
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lan_data {
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label = "orange:lan_data";
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gpios = <&gpio 15 GPIO_ACTIVE_LOW>;
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};
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lan_link {
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label = "green:lan_link";
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gpios = <&gpio 14 GPIO_ACTIVE_LOW>;
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};
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wifi_amber {
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label = "amber:wifi";
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gpios = <&gpio 19 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy1tpt";
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};
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wifi_green {
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label = "green:wifi";
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gpios = <&gpio 18 GPIO_ACTIVE_LOW>;
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linux,default-trigger = "phy0tpt";
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};
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};
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};
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&ref {
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clock-frequency = <25000000>;
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};
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ð0 {
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nvmem-cells = <&macaddr_art_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <(-2)>;
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};
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&pcie {
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status = "disabled";
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};
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&wmac {
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/delete-property/ qca,disable-2ghz;
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nvmem-cells = <&macaddr_art_0>;
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nvmem-cell-names = "mac-address";
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mac-address-increment = <(-2)>;
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};
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&art {
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compatible = "nvmem-cells";
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#address-cells = <1>;
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#size-cells = <1>;
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macaddr_art_0: macaddr@0 {
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reg = <0x0 0x6>;
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};
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};
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