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ed57a9f6a8
This is an automatically generated commit which aids following Kernel patch history, as git will see the move and copy as a rename thus defeating the purpose. See: https://lists.openwrt.org/pipermail/openwrt-devel/2023-October/041673.html for the original discussion. Signed-off-by: Mieczyslaw Nalewaj <namiltd@yahoo.com>
57 lines
2.2 KiB
Diff
57 lines
2.2 KiB
Diff
From 6e68dae946e3a0333fbde5487ce163142ca10ae0 Mon Sep 17 00:00:00 2001
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From: Nathan Chancellor <nathan@kernel.org>
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Date: Thu, 22 Jun 2023 15:56:19 +0000
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Subject: clk: ralink: mtmips: Fix uninitialized use of ret in
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mtmips_register_{fixed,factor}_clocks()
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Clang warns:
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drivers/clk/ralink/clk-mtmips.c:309:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
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309 | return ret;
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| ^~~
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drivers/clk/ralink/clk-mtmips.c:285:9: note: initialize the variable 'ret' to silence this warning
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285 | int ret, i;
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| ^
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| = 0
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drivers/clk/ralink/clk-mtmips.c:359:9: error: variable 'ret' is uninitialized when used here [-Werror,-Wuninitialized]
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359 | return ret;
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| ^~~
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drivers/clk/ralink/clk-mtmips.c:335:9: note: initialize the variable 'ret' to silence this warning
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335 | int ret, i;
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| ^
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| = 0
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2 errors generated.
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Set ret to the return value of clk_hw_register_fixed_rate() using the
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PTR_ERR() macro, which ensures ret is not used uninitialized, clearing
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up the warning.
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Fixes: 6f3b15586eef ("clk: ralink: add clock and reset driver for MTMIPS SoCs")
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Closes: https://github.com/ClangBuiltLinux/linux/issues/1879
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Signed-off-by: Nathan Chancellor <nathan@kernel.org>
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Reviewed-by: Nick Desaulniers <ndesaulniers@google.com>
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Acked-by: Sergio Paracuellos <sergio.paracuellos@gmail.com>
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Signed-off-by: Thomas Bogendoerfer <tsbogend@alpha.franken.de>
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---
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drivers/clk/ralink/clk-mtmips.c | 2 ++
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1 file changed, 2 insertions(+)
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--- a/drivers/clk/ralink/clk-mtmips.c
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+++ b/drivers/clk/ralink/clk-mtmips.c
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@@ -292,6 +292,7 @@ static int mtmips_register_fixed_clocks(
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sclk->parent, 0,
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sclk->rate);
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if (IS_ERR(sclk->hw)) {
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+ ret = PTR_ERR(sclk->hw);
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pr_err("Couldn't register fixed clock %d\n", idx);
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goto err_clk_unreg;
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}
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@@ -342,6 +343,7 @@ static int mtmips_register_factor_clocks
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sclk->parent, sclk->flags,
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sclk->mult, sclk->div);
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if (IS_ERR(sclk->hw)) {
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+ ret = PTR_ERR(sclk->hw);
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pr_err("Couldn't register factor clock %d\n", idx);
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goto err_clk_unreg;
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}
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