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99545b4bb1
This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
65 lines
2.8 KiB
Diff
65 lines
2.8 KiB
Diff
From 7708f7471ab45039e08237b42121d0372f9216a7 Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 13 Jun 2021 23:42:19 -0500
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Subject: [PATCH 043/117] hwspinlock: sun6i: Clarify bank counting logic
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In some of the most recent datasheets, the register definition was
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updated in a way that resolves the conflict here: the field is only two
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bits wide, and a value of "4" really means a bit pattern of "0". Correct
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the code to reflect this, but leave an updated comment because some
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datasheets still have incorrect information in them.
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Fixes: 3c881e05c814 ("hwspinlock: add sun6i hardware spinlock support")
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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drivers/hwspinlock/sun6i_hwspinlock.c | 36 +++++++++++----------------
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1 file changed, 14 insertions(+), 22 deletions(-)
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--- a/drivers/hwspinlock/sun6i_hwspinlock.c
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+++ b/drivers/hwspinlock/sun6i_hwspinlock.c
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@@ -129,30 +129,22 @@ static int sun6i_hwspinlock_probe(struct
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}
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/*
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- * bit 28 and 29 represents the hwspinlock setup
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+ * Bits 28 and 29 represent the number of available locks.
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*
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- * every datasheet (A64, A80, A83T, H3, H5, H6 ...) says the default value is 0x1 and 0x1
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- * to 0x4 represent 32, 64, 128 and 256 locks
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- * but later datasheets (H5, H6) say 00, 01, 10, 11 represent 32, 64, 128 and 256 locks,
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- * but that would mean H5 and H6 have 64 locks, while their datasheets talk about 32 locks
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- * all the time, not a single mentioning of 64 locks
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- * the 0x4 value is also not representable by 2 bits alone, so some datasheets are not
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- * correct
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- * one thing have all in common, default value of the sysstatus register is 0x10000000,
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- * which results in bit 28 being set
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- * this is the reason 0x1 is considered being 32 locks and bit 30 is taken into account
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- * verified on H2+ (datasheet 0x1 = 32 locks) and H5 (datasheet 01 = 64 locks)
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+ * The datasheets have two conflicting interpretations for these bits:
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+ * | 00 | 01 | 10 | 11 |
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+ * +-----+----+-----+-----+
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+ * | 256 | 32 | 64 | 128 | A80, A83T, H3, A64, A50, D1
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+ * | 32 | 64 | 128 | 256 | H5, H6, R329
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+ * where some datasheets use "4" instead of "0" for the first column.
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+ *
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+ * Experiments shows that the first interpretation is correct, as all
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+ * known implementations report the value "1" and have 32 spinlocks.
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*/
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- num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28;
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- switch (num_banks) {
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- case 1 ... 4:
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- priv->nlocks = 1 << (4 + num_banks);
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- break;
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- default:
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- err = -EINVAL;
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- dev_err(&pdev->dev, "unsupported hwspinlock setup (%d)\n", num_banks);
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- goto bank_fail;
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- }
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+ num_banks = readl(io_base + SPINLOCK_SYSSTATUS_REG) >> 28 & 0x3;
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+ if (!num_banks)
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+ num_banks = 4;
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+ priv->nlocks = 1 << (4 + num_banks);
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priv->bank = devm_kzalloc(&pdev->dev, struct_size(priv->bank, lock, priv->nlocks),
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GFP_KERNEL);
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