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This target adds support for the Allwinner D1 RISC-V based SoCs.
- RISC-V single-core T-Head C906 (RV64GCV)
- Tensilica HiFi4 DSP
- DDR2/DDR3 support
- 10/100/1000M ethernet
- usual peripherals like USB2, SPI, I2C, PWM, etc.
Four boards are supported:
- Dongshan Nezha STU
- 512Mb RAM
- ethernet
- LicheePi RV Dock
- 512Mb RAM
- wireless-only (RTL8723DS)
- MangoPi MQ-Pro
- 512Mb RAM
- there are pads available for an SPI flash
- wireless-only (RTL8723DS)
- Nezha D1
- 512Mb/1Gb/2Gb RAM
- 256Mb NAND flash
- ethernet, wireless
Installation:
Standard SD-card installation via dd-ing the generated image to
an SD-card of at least 256Mb.
Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
28 lines
935 B
Diff
28 lines
935 B
Diff
From 4ae663dbc373f5690581cee16d3667693eb9d73e Mon Sep 17 00:00:00 2001
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From: Samuel Holland <samuel@sholland.org>
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Date: Sun, 16 May 2021 14:05:17 -0500
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Subject: [PATCH 025/117] dt-bindings: riscv: Add T-HEAD C906 and C910
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compatibles
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The C906 and C910 are RISC-V CPU cores from T-HEAD Semiconductor.
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Notably, the C906 core is used in the Allwinner D1 SoC.
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Acked-by: Rob Herring <robh@kernel.org>
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Reviewed-by: Heiko Stuebner <heiko@sntech.de>
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Signed-off-by: Samuel Holland <samuel@sholland.org>
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---
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Documentation/devicetree/bindings/riscv/cpus.yaml | 2 ++
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1 file changed, 2 insertions(+)
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--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
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+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
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@@ -39,6 +39,8 @@ properties:
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- sifive,u5
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- sifive,u7
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- canaan,k210
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+ - thead,c906
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+ - thead,c910
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- const: riscv
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- items:
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- enum:
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