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ac422c9788
Changelog: https://cdn.kernel.org/pub/linux/kernel/v5.x/ChangeLog-5.15.132 Removed upstreamed: bcm53xx/patches-5.15/037-v6.6-0006-ARM-dts-BCM53573-Add-cells-sizes-to-PCIe-node.patch[1] bcm53xx/patches-5.15/037-v6.6-0007-ARM-dts-BCM53573-Use-updated-spi-gpio-binding-proper.patch[2] bcm53xx/patches-5.15/037-v6.6-0008-ARM-dts-BCM5301X-Extend-RAM-to-full-256MB-for-Linksy.patch[3] All other patches automatically rebased. 1. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.132&id=b35f3ca1877e024887df205ede952863d65dad36 2. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.132&id=2840d9b9c8750be270fb1153ccd5b983cbb5d592 3. https://git.kernel.org/pub/scm/linux/kernel/git/stable/linux.git/commit/?h=v5.15.132&id=f086e859ddc252c32f0438edff241859c0f022ce Build system: x86_64 Build-tested: ramips/tplink_archer-a6-v3 Run-tested: ramips/tplink_archer-a6-v3 Signed-off-by: John Audia <therealgraysky@proton.me>
38 lines
1.2 KiB
Diff
38 lines
1.2 KiB
Diff
From: Felix Fietkau <nbd@nbd.name>
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Date: Thu, 3 Nov 2022 17:46:25 +0100
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Subject: [PATCH] net: ethernet: mtk_eth_soc: drop packets to WDMA if the
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ring is full
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Improves handling of DMA ring overflow.
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Clarify other WDMA drop related comment.
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Signed-off-by: Felix Fietkau <nbd@nbd.name>
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---
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.c
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@@ -3715,9 +3715,12 @@ static int mtk_hw_init(struct mtk_eth *e
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mtk_w32(eth, 0x21021000, MTK_FE_INT_GRP);
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if (MTK_HAS_CAPS(eth->soc->caps, MTK_NETSYS_V2)) {
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- /* PSE should not drop port8 and port9 packets */
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+ /* PSE should not drop port8 and port9 packets from WDMA Tx */
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mtk_w32(eth, 0x00000300, PSE_DROP_CFG);
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+ /* PSE should drop packets to port 8/9 on WDMA Rx ring full */
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+ mtk_w32(eth, 0x00000300, PSE_PPE0_DROP);
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+
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/* PSE Free Queue Flow Control */
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mtk_w32(eth, 0x01fa01f4, PSE_FQFC_CFG2);
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--- a/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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+++ b/drivers/net/ethernet/mediatek/mtk_eth_soc.h
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@@ -140,6 +140,7 @@
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#define PSE_FQFC_CFG1 0x100
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#define PSE_FQFC_CFG2 0x104
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#define PSE_DROP_CFG 0x108
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+#define PSE_PPE0_DROP 0x110
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/* PSE Input Queue Reservation Register*/
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#define PSE_IQ_REV(x) (0x140 + (((x) - 1) << 2))
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