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0b000cbfe0
This patch backports "spi-realtek-rtl" driver to Kernel 5.10 from 5.12. "MACH_REALTEK_RTL" is used as a platform name in upstream, but "RTL838X" is used in OpenWrt, so update the dependency by the additional patch. Signed-off-by: INAGAKI Hiroshi <musashino.open@gmail.com>
249 lines
6.3 KiB
Diff
249 lines
6.3 KiB
Diff
From a8af5cc2ff1e804694629a8ef320935629dd15ba Mon Sep 17 00:00:00 2001
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From: Bert Vermeulen <bert@biot.com>
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Date: Wed, 20 Jan 2021 14:59:28 +0100
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Subject: spi: realtek-rtl: Add support for Realtek RTL838x/RTL839x SPI
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controllers
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This driver likely also supports earlier (RTL8196) and later (RTL93xx)
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SoCs.
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The SPI hardware in these SoCs is specifically intended for connecting NOR
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bootflash chips, and only used for that in dozens of examined devices.
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However boiled down to basics, it's really just a half-duplex SPI
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controller.
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The hardware appears to have a vestigial second chip-select control, but
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it hasn't been seen in the wild and is thus not supported.
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Signed-off-by: Bert Vermeulen <bert@biot.com>
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Link: https://lore.kernel.org/r/20210120135928.246054-3-bert@biot.com
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Signed-off-by: Mark Brown <broonie@kernel.org>
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---
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drivers/spi/Makefile | 1 +
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drivers/spi/spi-realtek-rtl.c | 209 ++++++++++++++++++++++++++++++++++++++++++
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2 files changed, 210 insertions(+)
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create mode 100644 drivers/spi/spi-realtek-rtl.c
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--- a/drivers/spi/Makefile
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+++ b/drivers/spi/Makefile
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@@ -94,6 +94,7 @@ obj-$(CONFIG_SPI_QCOM_QSPI) += spi-qcom
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obj-$(CONFIG_SPI_QUP) += spi-qup.o
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obj-$(CONFIG_SPI_ROCKCHIP) += spi-rockchip.o
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obj-$(CONFIG_SPI_RB4XX) += spi-rb4xx.o
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+obj-$(CONFIG_MACH_REALTEK_RTL) += spi-realtek-rtl.o
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obj-$(CONFIG_SPI_RPCIF) += spi-rpc-if.o
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obj-$(CONFIG_SPI_RSPI) += spi-rspi.o
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obj-$(CONFIG_SPI_S3C24XX) += spi-s3c24xx-hw.o
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--- /dev/null
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+++ b/drivers/spi/spi-realtek-rtl.c
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@@ -0,0 +1,209 @@
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+// SPDX-License-Identifier: GPL-2.0-only
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+
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+#include <linux/module.h>
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+#include <linux/platform_device.h>
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+#include <linux/mod_devicetable.h>
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+#include <linux/spi/spi.h>
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+
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+struct rtspi {
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+ void __iomem *base;
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+};
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+
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+/* SPI Flash Configuration Register */
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+#define RTL_SPI_SFCR 0x00
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+#define RTL_SPI_SFCR_RBO BIT(28)
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+#define RTL_SPI_SFCR_WBO BIT(27)
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+
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+/* SPI Flash Control and Status Register */
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+#define RTL_SPI_SFCSR 0x08
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+#define RTL_SPI_SFCSR_CSB0 BIT(31)
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+#define RTL_SPI_SFCSR_CSB1 BIT(30)
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+#define RTL_SPI_SFCSR_RDY BIT(27)
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+#define RTL_SPI_SFCSR_CS BIT(24)
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+#define RTL_SPI_SFCSR_LEN_MASK ~(0x03 << 28)
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+#define RTL_SPI_SFCSR_LEN1 (0x00 << 28)
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+#define RTL_SPI_SFCSR_LEN4 (0x03 << 28)
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+
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+/* SPI Flash Data Register */
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+#define RTL_SPI_SFDR 0x0c
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+
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+#define REG(x) (rtspi->base + x)
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+
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+
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+static void rt_set_cs(struct spi_device *spi, bool active)
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+{
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+ struct rtspi *rtspi = spi_controller_get_devdata(spi->controller);
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+ u32 value;
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+
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+ /* CS0 bit is active low */
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+ value = readl(REG(RTL_SPI_SFCSR));
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+ if (active)
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+ value |= RTL_SPI_SFCSR_CSB0;
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+ else
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+ value &= ~RTL_SPI_SFCSR_CSB0;
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+ writel(value, REG(RTL_SPI_SFCSR));
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+}
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+
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+static void set_size(struct rtspi *rtspi, int size)
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+{
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+ u32 value;
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+
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+ value = readl(REG(RTL_SPI_SFCSR));
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+ value &= RTL_SPI_SFCSR_LEN_MASK;
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+ if (size == 4)
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+ value |= RTL_SPI_SFCSR_LEN4;
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+ else if (size == 1)
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+ value |= RTL_SPI_SFCSR_LEN1;
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+ writel(value, REG(RTL_SPI_SFCSR));
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+}
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+
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+static inline void wait_ready(struct rtspi *rtspi)
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+{
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+ while (!(readl(REG(RTL_SPI_SFCSR)) & RTL_SPI_SFCSR_RDY))
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+ cpu_relax();
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+}
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+static void send4(struct rtspi *rtspi, const u32 *buf)
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+{
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+ wait_ready(rtspi);
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+ set_size(rtspi, 4);
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+ writel(*buf, REG(RTL_SPI_SFDR));
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+}
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+
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+static void send1(struct rtspi *rtspi, const u8 *buf)
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+{
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+ wait_ready(rtspi);
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+ set_size(rtspi, 1);
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+ writel(buf[0] << 24, REG(RTL_SPI_SFDR));
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+}
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+
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+static void rcv4(struct rtspi *rtspi, u32 *buf)
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+{
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+ wait_ready(rtspi);
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+ set_size(rtspi, 4);
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+ *buf = readl(REG(RTL_SPI_SFDR));
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+}
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+
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+static void rcv1(struct rtspi *rtspi, u8 *buf)
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+{
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+ wait_ready(rtspi);
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+ set_size(rtspi, 1);
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+ *buf = readl(REG(RTL_SPI_SFDR)) >> 24;
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+}
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+
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+static int transfer_one(struct spi_controller *ctrl, struct spi_device *spi,
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+ struct spi_transfer *xfer)
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+{
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+ struct rtspi *rtspi = spi_controller_get_devdata(ctrl);
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+ void *rx_buf;
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+ const void *tx_buf;
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+ int cnt;
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+
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+ tx_buf = xfer->tx_buf;
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+ rx_buf = xfer->rx_buf;
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+ cnt = xfer->len;
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+ if (tx_buf) {
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+ while (cnt >= 4) {
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+ send4(rtspi, tx_buf);
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+ tx_buf += 4;
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+ cnt -= 4;
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+ }
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+ while (cnt) {
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+ send1(rtspi, tx_buf);
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+ tx_buf++;
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+ cnt--;
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+ }
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+ } else if (rx_buf) {
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+ while (cnt >= 4) {
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+ rcv4(rtspi, rx_buf);
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+ rx_buf += 4;
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+ cnt -= 4;
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+ }
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+ while (cnt) {
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+ rcv1(rtspi, rx_buf);
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+ rx_buf++;
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+ cnt--;
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+ }
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+ }
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+
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+ spi_finalize_current_transfer(ctrl);
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+
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+ return 0;
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+}
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+
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+static void init_hw(struct rtspi *rtspi)
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+{
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+ u32 value;
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+
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+ /* Turn on big-endian byte ordering */
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+ value = readl(REG(RTL_SPI_SFCR));
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+ value |= RTL_SPI_SFCR_RBO | RTL_SPI_SFCR_WBO;
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+ writel(value, REG(RTL_SPI_SFCR));
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+
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+ value = readl(REG(RTL_SPI_SFCSR));
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+ /* Permanently disable CS1, since it's never used */
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+ value |= RTL_SPI_SFCSR_CSB1;
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+ /* Select CS0 for use */
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+ value &= RTL_SPI_SFCSR_CS;
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+ writel(value, REG(RTL_SPI_SFCSR));
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+}
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+
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+static int realtek_rtl_spi_probe(struct platform_device *pdev)
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+{
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+ struct spi_controller *ctrl;
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+ struct rtspi *rtspi;
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+ int err;
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+
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+ ctrl = devm_spi_alloc_master(&pdev->dev, sizeof(*rtspi));
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+ if (!ctrl) {
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+ dev_err(&pdev->dev, "Error allocating SPI controller\n");
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+ return -ENOMEM;
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+ }
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+ platform_set_drvdata(pdev, ctrl);
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+ rtspi = spi_controller_get_devdata(ctrl);
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+
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+ rtspi->base = devm_platform_get_and_ioremap_resource(pdev, 0, NULL);
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+ if (IS_ERR(rtspi->base)) {
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+ dev_err(&pdev->dev, "Could not map SPI register address");
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+ return -ENOMEM;
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+ }
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+
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+ init_hw(rtspi);
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+
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+ ctrl->dev.of_node = pdev->dev.of_node;
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+ ctrl->flags = SPI_CONTROLLER_HALF_DUPLEX;
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+ ctrl->set_cs = rt_set_cs;
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+ ctrl->transfer_one = transfer_one;
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+
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+ err = devm_spi_register_controller(&pdev->dev, ctrl);
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+ if (err) {
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+ dev_err(&pdev->dev, "Could not register SPI controller\n");
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+ return -ENODEV;
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+ }
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+
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+ return 0;
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+}
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+
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+
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+static const struct of_device_id realtek_rtl_spi_of_ids[] = {
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+ { .compatible = "realtek,rtl8380-spi" },
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+ { .compatible = "realtek,rtl8382-spi" },
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+ { .compatible = "realtek,rtl8391-spi" },
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+ { .compatible = "realtek,rtl8392-spi" },
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+ { .compatible = "realtek,rtl8393-spi" },
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+ { /* sentinel */ }
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+};
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+MODULE_DEVICE_TABLE(of, realtek_rtl_spi_of_ids);
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+
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+static struct platform_driver realtek_rtl_spi_driver = {
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+ .probe = realtek_rtl_spi_probe,
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+ .driver = {
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+ .name = "realtek-rtl-spi",
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+ .of_match_table = realtek_rtl_spi_of_ids,
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+ },
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+};
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+
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+module_platform_driver(realtek_rtl_spi_driver);
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+
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+MODULE_LICENSE("GPL v2");
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+MODULE_AUTHOR("Bert Vermeulen <bert@biot.com>");
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+MODULE_DESCRIPTION("Realtek RTL SPI driver");
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