mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-29 01:59:02 +00:00
9a1d7ff187
Refreshed all patches. Remove upstreamed: - 950-0434-mmc-bcm2835-Recover-from-MMC_SEND_EXT_CSD.patch Compile-tested on: ar71xx, cns3xxx, imx6, x86_64 Runtime-tested on: ar71xx, cns3xxx, imx6 Signed-off-by: Koen Vandeputte <koen.vandeputte@ncentric.com>
49 lines
1.8 KiB
Diff
49 lines
1.8 KiB
Diff
From 82f8b13481afeb2400bce276cf88a757fac87a21 Mon Sep 17 00:00:00 2001
|
|
From: Eric Anholt <eric@anholt.net>
|
|
Date: Fri, 14 Jul 2017 17:33:08 -0700
|
|
Subject: [PATCH 131/454] drm/vc4: Fix pitch setup for T-format scanout.
|
|
|
|
The documentation said to use src_w here, and I didn't consider that
|
|
we actually needed to be using pitch somewhere in our setup. Fixes
|
|
scanout on my DSI panel when X11 does initial setup with 1920x1080
|
|
HDMI and 800x480 DSI both at 0,0 of the same framebuffer.
|
|
|
|
Signed-off-by: Eric Anholt <eric@anholt.net>
|
|
Fixes: 98830d91da08 ("drm/vc4: Add T-format scanout support.")
|
|
---
|
|
drivers/gpu/drm/vc4/vc4_plane.c | 20 +++++++++++++++-----
|
|
1 file changed, 15 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/gpu/drm/vc4/vc4_plane.c
|
|
+++ b/drivers/gpu/drm/vc4/vc4_plane.c
|
|
@@ -549,14 +549,24 @@ static int vc4_plane_mode_set(struct drm
|
|
tiling = SCALER_CTL0_TILING_LINEAR;
|
|
pitch0 = VC4_SET_FIELD(fb->pitches[0], SCALER_SRC_PITCH);
|
|
break;
|
|
- case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED:
|
|
+
|
|
+ case DRM_FORMAT_MOD_BROADCOM_VC4_T_TILED: {
|
|
+ /* For T-tiled, the FB pitch is "how many bytes from
|
|
+ * one row to the next, such that pitch * tile_h ==
|
|
+ * tile_size * tiles_per_row."
|
|
+ */
|
|
+ u32 tile_size_shift = 12;
|
|
+ u32 tile_h_shift = 5;
|
|
+ u32 tiles_w = fb->pitches[0] >> (tile_size_shift - tile_h_shift);
|
|
+
|
|
tiling = SCALER_CTL0_TILING_256B_OR_T;
|
|
|
|
- pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET),
|
|
- VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L),
|
|
- VC4_SET_FIELD((vc4_state->src_w[0] + 31) >> 5,
|
|
- SCALER_PITCH0_TILE_WIDTH_R));
|
|
+ pitch0 = (VC4_SET_FIELD(0, SCALER_PITCH0_TILE_Y_OFFSET) |
|
|
+ VC4_SET_FIELD(0, SCALER_PITCH0_TILE_WIDTH_L) |
|
|
+ VC4_SET_FIELD(tiles_w, SCALER_PITCH0_TILE_WIDTH_R));
|
|
break;
|
|
+ }
|
|
+
|
|
default:
|
|
DRM_DEBUG_KMS("Unsupported FB tiling flag 0x%16llx",
|
|
(long long)fb->modifier);
|