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cb42c2e307
Backport Aquantia PHY endianess patch. While the current implementation works ok for Little-Endian targets, backport patch to prevent any kind of malfunction if in the future we will have Big-Endian target with Aquantia PHYs. Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
93 lines
3.8 KiB
Diff
93 lines
3.8 KiB
Diff
From 7edce370d87a23e8ed46af5b76a9fef1e341b67b Mon Sep 17 00:00:00 2001
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From: Christian Marangi <ansuelsmth@gmail.com>
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Date: Tue, 28 Nov 2023 14:59:28 +0100
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Subject: [PATCH] net: phy: aquantia: drop wrong endianness conversion for addr
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and CRC
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On further testing on BE target with kernel test robot, it was notice
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that the endianness conversion for addr and CRC in fw_load_memory was
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wrong.
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Drop the cpu_to_le32 conversion for addr load as it's not needed.
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Use get_unaligned_le32 instead of get_unaligned for FW data word load to
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correctly convert data in the correct order to follow system endian.
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Also drop the cpu_to_be32 for CRC calculation as it's wrong and would
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cause different CRC on BE system.
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The loaded word is swapped internally and MAILBOX calculates the CRC on
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the swapped word. To correctly calculate the CRC to be later matched
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with the one from MAILBOX, use an u8 struct and swap the word there to
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keep the same order on both LE and BE for crc_ccitt_false function.
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Also add additional comments on how the CRC verification for the loaded
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section works.
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CRC is calculated as we load the section and verified with the MAILBOX
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only after the entire section is loaded to skip additional slowdown by
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loop the section data again.
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Reported-by: kernel test robot <lkp@intel.com>
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Closes: https://lore.kernel.org/oe-kbuild-all/202311210414.sEJZjlcD-lkp@intel.com/
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Fixes: e93984ebc1c8 ("net: phy: aquantia: add firmware load support")
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Tested-by: Robert Marko <robimarko@gmail.com> # ipq8072 LE device
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Signed-off-by: Christian Marangi <ansuelsmth@gmail.com>
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Link: https://lore.kernel.org/r/20231128135928.9841-1-ansuelsmth@gmail.com
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Signed-off-by: Jakub Kicinski <kuba@kernel.org>
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---
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drivers/net/phy/aquantia/aquantia_firmware.c | 24 ++++++++++++--------
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1 file changed, 14 insertions(+), 10 deletions(-)
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--- a/drivers/net/phy/aquantia/aquantia_firmware.c
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+++ b/drivers/net/phy/aquantia/aquantia_firmware.c
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@@ -93,9 +93,6 @@ static int aqr_fw_load_memory(struct phy
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u16 crc = 0, up_crc;
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size_t pos;
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- /* PHY expect addr in LE */
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- addr = (__force u32)cpu_to_le32(addr);
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-
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phy_write_mmd(phydev, MDIO_MMD_VEND1,
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VEND1_GLOBAL_MAILBOX_INTERFACE1,
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VEND1_GLOBAL_MAILBOX_INTERFACE1_CRC_RESET);
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@@ -110,10 +107,11 @@ static int aqr_fw_load_memory(struct phy
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* If a firmware that is not word aligned is found, please report upstream.
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*/
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for (pos = 0; pos < len; pos += sizeof(u32)) {
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+ u8 crc_data[4];
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u32 word;
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/* FW data is always stored in little-endian */
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- word = get_unaligned((const u32 *)(data + pos));
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+ word = get_unaligned_le32((const u32 *)(data + pos));
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phy_write_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE5,
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VEND1_GLOBAL_MAILBOX_INTERFACE5_MSW_DATA(word));
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@@ -124,15 +122,21 @@ static int aqr_fw_load_memory(struct phy
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VEND1_GLOBAL_MAILBOX_INTERFACE1_EXECUTE |
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VEND1_GLOBAL_MAILBOX_INTERFACE1_WRITE);
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- /* calculate CRC as we load data to the mailbox.
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- * We convert word to big-endian as PHY is BE and mailbox will
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- * return a BE CRC.
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+ /* Word is swapped internally and MAILBOX CRC is calculated
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+ * using big-endian order. Mimic what the PHY does to have a
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+ * matching CRC...
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*/
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- word = (__force u32)cpu_to_be32(word);
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- crc = crc_ccitt_false(crc, (u8 *)&word, sizeof(word));
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- }
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+ crc_data[0] = word >> 24;
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+ crc_data[1] = word >> 16;
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+ crc_data[2] = word >> 8;
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+ crc_data[3] = word;
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+ /* ...calculate CRC as we load data... */
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+ crc = crc_ccitt_false(crc, crc_data, sizeof(crc_data));
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+ }
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+ /* ...gets CRC from MAILBOX after we have loaded the entire section... */
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up_crc = phy_read_mmd(phydev, MDIO_MMD_VEND1, VEND1_GLOBAL_MAILBOX_INTERFACE2);
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+ /* ...and make sure it does match our calculated CRC */
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if (crc != up_crc) {
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phydev_err(phydev, "CRC mismatch: calculated 0x%04x PHY 0x%04x\n",
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crc, up_crc);
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