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4070e2a64c
This target adds support for the StarFive JH7100 and JH7110 SoCs, based on 6.1, as well as a couple boards equipped with these. Specifications: SoCs: JH7100: - StarFive JH7100 dual-core RISC-V (U74, RC64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache JH7110: - StarFive JH7110 quad-core RISC-V (U74, RV64GC) - additional monitoring (S7) and control (E24) cores - 2Mb L2 cache Boards: VisionFive1: - JH7100 @ 1GHz - Memory: 8Gb LPDDR4 - 4x USB3.0 - 1x GBit ethernet - AMPak 6236 wifi / bluetooth - audio - powered via USB-C VisionFive2: - JH7110 @ 1.5GHz - Memory: 2/4/8Gb DDR4 - 2x Gbit ethernet - 2x USB3.0 / 2x USB2.0 - eMMC / SDIO - various multimedia input/outputs (MIPI CSI, HDMI, audio) - M.2 key M slot - PoE support - powered via USB-C Installation: Standard SD-card installation via dd-ing the generated image to an SD-card of at least 256Mb. Signed-off-by: Zoltan HERPAI <wigyori@uid0.hu>
128 lines
4.2 KiB
Diff
128 lines
4.2 KiB
Diff
From 89c86fda8cee5b93ce213dcc46b2cf27e5ee3312 Mon Sep 17 00:00:00 2001
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From: Emil Renner Berthing <kernel@esmil.dk>
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Date: Sat, 17 Jul 2021 21:50:38 +0200
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Subject: [PATCH 1009/1024] pinctrl: starfive: Reset pinmux settings
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Current u-boot doesn't seem to take into account that some GPIOs are
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configured as inputs/outputs of certain peripherals on power-up. This
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means it ends up configuring some GPIOs as inputs to more than one
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peripheral which the documentation explicitly says is illegal. Similarly
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it also ends up configuring more than one GPIO as output of the same
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peripheral. While not explicitly mentioned by the documentation this
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also seems like a bad idea.
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The easiest way to remedy this mess is to just disconnect all GPIOs from
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peripherals and have our pinmux configuration set everything up
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properly. This, however, means that we'd disconnect the serial console
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from its pins for a while, so add a device tree property to keep
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certain GPIOs from being reset.
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Signed-off-by: Emil Renner Berthing <kernel@esmil.dk>
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---
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.../pinctrl/starfive,jh7100-pinctrl.yaml | 4 ++
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.../starfive/pinctrl-starfive-jh7100.c | 66 +++++++++++++++++++
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2 files changed, 70 insertions(+)
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--- a/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
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+++ b/Documentation/devicetree/bindings/pinctrl/starfive,jh7100-pinctrl.yaml
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@@ -88,6 +88,10 @@ properties:
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$ref: /schemas/types.yaml#/definitions/uint32
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enum: [0, 1, 2, 3, 4, 5, 6]
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+ starfive,keep-gpiomux:
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+ description: Keep pinmux for these GPIOs from being reset at boot.
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+ $ref: /schemas/types.yaml#/definitions/uint32-array
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+
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required:
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- compatible
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- reg
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--- a/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
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+++ b/drivers/pinctrl/starfive/pinctrl-starfive-jh7100.c
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@@ -200,6 +200,10 @@ static u16 starfive_drive_strength_from_
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return (clamp(i, 14U, 63U) - 14) / 7;
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}
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+static bool keepmux;
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+module_param(keepmux, bool, 0644);
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+MODULE_PARM_DESC(keepmux, "Keep pinmux settings from previous boot stage");
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+
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struct starfive_pinctrl {
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struct gpio_chip gc;
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struct pinctrl_gpio_range gpios;
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@@ -1222,6 +1226,65 @@ static void starfive_disable_clock(void
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clk_disable_unprepare(data);
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}
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+#define GPI_END (GPI_USB_OVER_CURRENT + 1)
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+static void starfive_pinmux_reset(struct starfive_pinctrl *sfp)
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+{
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+ static const DECLARE_BITMAP(defaults, GPI_END) = {
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+ BIT_MASK(GPI_I2C0_PAD_SCK_IN) |
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+ BIT_MASK(GPI_I2C0_PAD_SDA_IN) |
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+ BIT_MASK(GPI_I2C1_PAD_SCK_IN) |
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+ BIT_MASK(GPI_I2C1_PAD_SDA_IN) |
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+ BIT_MASK(GPI_I2C2_PAD_SCK_IN) |
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+ BIT_MASK(GPI_I2C2_PAD_SDA_IN) |
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+ BIT_MASK(GPI_I2C3_PAD_SCK_IN) |
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+ BIT_MASK(GPI_I2C3_PAD_SDA_IN) |
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+ BIT_MASK(GPI_SDIO0_PAD_CARD_DETECT_N) |
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+
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+ BIT_MASK(GPI_SDIO1_PAD_CARD_DETECT_N) |
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+ BIT_MASK(GPI_SPI0_PAD_SS_IN_N) |
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+ BIT_MASK(GPI_SPI1_PAD_SS_IN_N) |
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+ BIT_MASK(GPI_SPI2_PAD_SS_IN_N) |
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+ BIT_MASK(GPI_SPI2AHB_PAD_SS_N) |
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+ BIT_MASK(GPI_SPI3_PAD_SS_IN_N),
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+
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+ BIT_MASK(GPI_UART0_PAD_SIN) |
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+ BIT_MASK(GPI_UART1_PAD_SIN) |
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+ BIT_MASK(GPI_UART2_PAD_SIN) |
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+ BIT_MASK(GPI_UART3_PAD_SIN) |
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+ BIT_MASK(GPI_USB_OVER_CURRENT)
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+ };
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+ DECLARE_BITMAP(keep, NR_GPIOS) = {};
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+ struct device_node *np = sfp->gc.parent->of_node;
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+ int len = of_property_count_u32_elems(np, "starfive,keep-gpiomux");
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+ int i;
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+
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+ for (i = 0; i < len; i++) {
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+ u32 gpio;
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+
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+ of_property_read_u32_index(np, "starfive,keep-gpiomux", i, &gpio);
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+ if (gpio < NR_GPIOS)
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+ set_bit(gpio, keep);
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+ }
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+
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+ for (i = 0; i < NR_GPIOS; i++) {
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+ if (test_bit(i, keep))
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+ continue;
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+
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+ writel_relaxed(GPO_DISABLE, sfp->base + GPON_DOEN_CFG + 8 * i);
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+ writel_relaxed(GPO_LOW, sfp->base + GPON_DOUT_CFG + 8 * i);
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+ }
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+
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+ for (i = 0; i < GPI_END; i++) {
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+ void __iomem *reg = sfp->base + GPI_CFG_OFFSET + 4 * i;
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+ u32 din = readl_relaxed(reg);
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+
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+ if (din >= 2 && din < (NR_GPIOS + 2) && test_bit(din - 2, keep))
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+ continue;
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+
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+ writel_relaxed(test_bit(i, defaults), reg);
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+ }
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+}
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+
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static int starfive_probe(struct platform_device *pdev)
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{
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struct device *dev = &pdev->dev;
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@@ -1283,6 +1346,9 @@ static int starfive_probe(struct platfor
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writel(value, sfp->padctl + IO_PADSHARE_SEL);
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}
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+ if (!keepmux)
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+ starfive_pinmux_reset(sfp);
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+
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value = readl(sfp->padctl + IO_PADSHARE_SEL);
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switch (value) {
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case 0:
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