mirror of
https://github.com/openwrt/openwrt.git
synced 2024-12-21 14:37:57 +00:00
68 lines
2.5 KiB
Diff
68 lines
2.5 KiB
Diff
From 40da06da15c1718b02072687bbfb2d08f5eb9399 Mon Sep 17 00:00:00 2001
|
|
From: =?UTF-8?q?Pali=20Roh=C3=A1r?= <pali@kernel.org>
|
|
Date: Fri, 27 Aug 2021 11:27:52 +0200
|
|
Subject: [PATCH] phy: marvell: phy-mvebu-a3700-comphy: Rename HS-SGMMI to
|
|
2500Base-X
|
|
MIME-Version: 1.0
|
|
Content-Type: text/plain; charset=UTF-8
|
|
Content-Transfer-Encoding: 8bit
|
|
|
|
Comphy phy mode 0x3 is incorrectly named. It is not SGMII but rather
|
|
2500Base-X mode which runs at 3.125 Gbps speed.
|
|
|
|
Rename macro names and comments to 2500Base-X.
|
|
|
|
Signed-off-by: Pali Rohár <pali@kernel.org>
|
|
Fixes: 9695375a3f4a ("phy: add A3700 COMPHY support")
|
|
Signed-off-by: David S. Miller <davem@davemloft.net>
|
|
---
|
|
drivers/phy/marvell/phy-mvebu-a3700-comphy.c | 10 +++++-----
|
|
1 file changed, 5 insertions(+), 5 deletions(-)
|
|
|
|
--- a/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
+++ b/drivers/phy/marvell/phy-mvebu-a3700-comphy.c
|
|
@@ -29,7 +29,7 @@
|
|
|
|
#define COMPHY_FW_MODE_SATA 0x1
|
|
#define COMPHY_FW_MODE_SGMII 0x2
|
|
-#define COMPHY_FW_MODE_HS_SGMII 0x3
|
|
+#define COMPHY_FW_MODE_2500BASEX 0x3
|
|
#define COMPHY_FW_MODE_USB3H 0x4
|
|
#define COMPHY_FW_MODE_USB3D 0x5
|
|
#define COMPHY_FW_MODE_PCIE 0x6
|
|
@@ -40,7 +40,7 @@
|
|
|
|
#define COMPHY_FW_SPEED_1_25G 0 /* SGMII 1G */
|
|
#define COMPHY_FW_SPEED_2_5G 1
|
|
-#define COMPHY_FW_SPEED_3_125G 2 /* SGMII 2.5G */
|
|
+#define COMPHY_FW_SPEED_3_125G 2 /* 2500BASE-X */
|
|
#define COMPHY_FW_SPEED_5G 3
|
|
#define COMPHY_FW_SPEED_5_15625G 4 /* XFI 5G */
|
|
#define COMPHY_FW_SPEED_6G 5
|
|
@@ -84,14 +84,14 @@ static const struct mvebu_a3700_comphy_c
|
|
MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_SGMII, 1,
|
|
COMPHY_FW_MODE_SGMII),
|
|
MVEBU_A3700_COMPHY_CONF_ETH(0, PHY_INTERFACE_MODE_2500BASEX, 1,
|
|
- COMPHY_FW_MODE_HS_SGMII),
|
|
+ COMPHY_FW_MODE_2500BASEX),
|
|
/* lane 1 */
|
|
MVEBU_A3700_COMPHY_CONF_GEN(1, PHY_MODE_PCIE, 0,
|
|
COMPHY_FW_MODE_PCIE),
|
|
MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_SGMII, 0,
|
|
COMPHY_FW_MODE_SGMII),
|
|
MVEBU_A3700_COMPHY_CONF_ETH(1, PHY_INTERFACE_MODE_2500BASEX, 0,
|
|
- COMPHY_FW_MODE_HS_SGMII),
|
|
+ COMPHY_FW_MODE_2500BASEX),
|
|
/* lane 2 */
|
|
MVEBU_A3700_COMPHY_CONF_GEN(2, PHY_MODE_SATA, 0,
|
|
COMPHY_FW_MODE_SATA),
|
|
@@ -205,7 +205,7 @@ static int mvebu_a3700_comphy_power_on(s
|
|
COMPHY_FW_SPEED_1_25G);
|
|
break;
|
|
case PHY_INTERFACE_MODE_2500BASEX:
|
|
- dev_dbg(lane->dev, "set lane %d to HS SGMII mode\n",
|
|
+ dev_dbg(lane->dev, "set lane %d to 2500BASEX mode\n",
|
|
lane->id);
|
|
fw_param = COMPHY_FW_NET(fw_mode, lane->port,
|
|
COMPHY_FW_SPEED_3_125G);
|